Register file with improved noise immunity and aspect ratio

Details Register file with improved noise immunity and aspect ratio Register file with improved noise immunity and aspect ratio

1999-11-22

2001-08-28

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

C365S230060

Reexamination Certificate

active

06282139

ABSTRACT:

BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to the general field of electronic circuits. More specifically the present invention relates to electronic memories.
II. Background Information
Most large digital chips such as modern microprocessors require register files for fast access to data. As the number of ports and word width in the chip increases, and as metal interconnect layers scale down in size and distance to the driving transistors increases, the distance between wordlines decreases. A decrease in the distance between wordlines causes the capacitance between wordlines to increase. The increased capacitance of wordlines contributes to reduction in the noise immunity of the register file as may be understood from the following description presented in connection with FIG.
1
.
FIG. 1
illustrates a plurality of wordlines
102
,
104
and
106
of a register file. Metal lines
102
,
104
and
106
have a line-to-line capacitance CLL there between. This capacitance dramatically increases when lines
102
,
104
and
106
get very close to each other. In sub-micron integrated circuits, the distance between wordlines has scaled below ½ &mgr;m. As the width of the memory increases, e.g., while data paths grow from 32 to 64 bits or as parts are added to the design, the distance to the driving transistors increases, effectively shielding the driver strength by increasing line resistance.
Assume that wordlines
102
and
106
go high in an upward transition of the signals therethrough from 0 to 1, while wordline
104
is supposed to stay low. Due to the line-to-line capacitance CLL, wordline
104
may charge up to a value that may exceed the threshold voltage V
t
of a transistor coupled to this line thereby causing that transistor to erroneously turn on. This would correspond to transistor
212
in
FIG. 2
turning on and allowing an erroneous read current to be placed on bitline
206
. As a consequence, a circuit connected to the wordline
104
may read at a time when it is not supposed to do so. Another problem with modern integrated circuits is that the threshold voltage V
t
has been decreasing over time, in part, due to the reduction in the size (sub-micron size) of the features in these circuits at the same time that the coupling is increasing. This makes the problem related to noise immunity worse.
SUMMARY OF THE INVENTION
A register file with a plurality of memory cells arranged such that a single word line enable signal path is coupled to word pairs formed from the memory cells, and a logic circuit which is configured to enable separate access of each word of the word pairs.


REFERENCES:
patent: 5392411 (1995-02-01), Ozaki
patent: 5978904 (1999-11-01), Matsuo et al.

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