Filter circuit

Details Filter circuit Filter circuit

1999-10-15

2001-05-29

Pascal, Robert (Department: 2817)

Amplifiers

With periodic switching input-output

C330S303000, C327S554000

Reexamination Certificate

active

06239654

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a filter circuit comprising an operation transconductance amplifier (OTA) and more particularly to a filter circuit capable of changing a variable range of a cut-off frequency operation transconductance amplifier.
BACKGROUND OF THE INVENTION
Conventionally, in LSIs for RF band signal processing for mobile transmission, a filter circuit is used in which time constant is constituted not of a resistor as a discrete element and a capacitor but an operation transconductance amplifier (OTA) and a capacitor. Further, an integrated filter circuit having a general purpose property intensified by adding a cut-off frequency automatic adjustment circuit capable of automatic adjustment of the cut-off frequency is often employed in such a filter.
FIG. 5
shows a circuit diagram of a conventional filter circuit having a OTA and the cut-off frequency automatic adjustment circuit, used in an analog signal processing system. Referring to
FIG. 5
, the conventional filter circuit comprises OTA
101
, OTA
102
, capacitor
111
(capacitance C
110
), capacitor
112
(capacitance C
120
) and the cut-off frequency automatic adjustment circuit
200
. A resistor
201
and a capacitor
202
, which are external adjustment elements, are connected to the cut-off frequency automatic adjustment circuit
200
.
In the OTA
101
, a signal which is an object for filtering is inputted through a positive phase input terminal N
100
and an output terminal thereof is connected to the positive phase input terminal of the OTA
102
. An output terminal of the OTA
102
is connected to inverse phase input terminals of the OTA
101
and OTA
102
. The OTA
101
and OTA
102
receive a signal outputted from the cut-off frequency automatic adjustment circuit
200
as a bias voltage. As a result, the OTA
101
and OTA
102
function as active loads of high input impedance and low output impedance.
The aforementioned capacitor
111
a terminal of which is grounded is connected to the output terminal of the OTA
101
and similarly the aforementioned capacitor
112
a terminal of which is grounded is connected to the output terminal of the OTA
102
. Therefore, the filter section is constituted of the OTA
101
as an active load and the capacitor
111
, and the OTA
102
as an active load and the capacitor
112
, and a filtered signal can be outputted from the output terminal of the OTA
102
. The frequency characteristic of this filter section is determined by the transconductances of the OTA
101
and OTA
102
and the capacitances of the capacitors
111
,
112
.
FIG. 6
is a circuit diagram common to the OTA
101
and OTA
102
and specifically indicates a differential amplification circuit section. The differential amplification circuit section shown in
FIG. 6
comprises a P-channel type MOS transistor M
10
for supplying a constant current to a pair of the differential transistors described below by inputting the bias voltage VB, a P-channel type MOS transistor M
11
and a P-channel type MOS transistor M
12
, both acting as a pair of the differential transistors, and a N-channel type MOS transistor M
13
and a N-channel type MOS transistor M
14
, both constituting a current mirror circuit functioning as an active load on the amplifier.
In this differential amplifying circuit section, a source of the MOS transistor M
10
is connected to a power line which supplies a power voltage Vdd (high level voltage) and a gate thereof is connected to a terminal which supplies the bias voltage VB. In the MOS transistor M
11
and MOS transistor M
12
, sources thereof are connected to each other, thereby constituting a pair of the differential transistor. Further, the sources of the MOS transistor M
11
and MOS transistor M
12
are connected to a drain of the MOS transistor M
10
, so that a current supplied through the MOS transistor M
10
is supplied to the pair of the differential transistors constituted of the aforementioned MOS transistor M
11
and MOS transistor M
12
.
A gate of the MOS transistor M
11
is connected to an input node N
190
of this differential amplification circuit section, namely to positive phase input terminals of the OTA
101
or OTA
102
. Specifically, the gate of the MOS transistor M
11
is connected to terminal N
100
in the OTA
101
from where a signal which is an object for filtering is inputted. Further, a gate of the MOS transistor M
12
is connected to the other input terminal N
200
of the differential amplification circuit section, namely to inverse phase input terminal of the OTA
101
or OTA
102
.
The gates of the MOS transistor M
13
and MOS transistor M
14
are connected to each other. The gate and drain of the MOS transistor M
13
are connected to form a current mirror circuit. Sources of the MOS transistor M
13
and MOS transistor M
14
are connected to a line of grounding voltage Vss (low level voltage).
A difference between signals inputted into the input node N
190
and input node N
200
is amplified by this differential amplification circuit section. The amplified signal is outputted from the input node N
210
connected to the drain of the MOS transistor M
12
as an output signal. In the OTA
101
and OTA
102
, because the respective inverse phase input terminals thereof corresponding to the input node N
200
are connected to the output terminal of the OTA
102
a negative feedback loop with gain
1
is formed, thereby the OTA
101
and OTA
102
act as an active load.
On the other hand,
FIG. 7
is a circuit diagram showing a structure of the cut-off frequency automatic adjustment circuit. The cut-off frequency automatic adjustment circuit
200
shown in
FIG. 7
comprises an OTA
103
having the same structure as the aforementioned OTA
101
and
102
, a comparator
240
and a sample hold circuit
300
. The positive phase input terminal (+) of the OTA
103
is connected to a contact terminal of each of the analog switches
221
,
222
and its inverse phase input terminal (−) is connected to an output node for dividing a voltage supplied from the power line by resistors
213
,
214
connected in series, namely a joint between the resistors
213
and
214
.
The other contact terminal of the analog switch
221
is connected to an output node for dividing a voltage supplied from the power line by the resistors
211
,
212
connected in series, namely a joint between the resistors
211
and
212
. The other contact terminal of the analog switch
222
is grounded.
The analog switch
221
inputs a clock CK
1
into the N-channel type MOS transistor and a clock CK
1
i
into the P-channel type MOS transistor as a change-over signal. The analog switch
222
inputs a clock CK
1
i
into the N-channel type MOS transistor and a clock CK
1
into the P-channel type MOS transistor side as a change-over signal.
The clock CK
1
is a clock inputted from the clock input terminal N
120
and the clock CK
1
i
is a signal obtained by inverting the input of the clock CK
1
by an inverter
251
as shown in the Figure. As a result, the analog switches
221
,
222
are turned ON/OFF complementarily by the clocks CK
1
, CK
1
i.
Thus, in the OTA
103
, a partial value supplied by the resistors
213
,
214
is inputted into the inverse phase input terminal as a reference voltage and then, a signal changed over by the clock CK
1
or either a partial voltage supplied by the resistors
213
,
214
or grounding voltage is inputted into the positive phase input terminal and a signal based on a difference between these signals is outputted. Further, the OTA
103
receives a voltage determined by the sample hold circuit
300
, which will be described later, and the resistor
201
and capacitor
202
, which are the aforementioned external adjustment devices, as the bias voltage VB.
One of the terminals of a capacitor
231
(capacitance C
100
) and a contact terminal of the analog switch
223
are connected to an output terminal of the OTA
103
. The other terminal of the capacitor
231
is grounded. The analog switch
223
inputs a clock CK
2
into the N-c

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