Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
1998-10-21
2001-07-03
Williams, Alexander O. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S700000, C257S758000, C257S701000, C257S752000, C257S774000, C257S773000, C257S760000, C257S759000, C257S738000, C257S786000, C257S737000, C257S208000, C257S635000
Reexamination Certificate
active
06255737
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and method of making the same, a circuit board, and an electronic instrument, and in particular relates to a semiconductor device having a package size close to the chip size and a method of making the same, a circuit board, and an electronic instrument.
BACKGROUND ART
To pursue high-density mounting in semiconductor devices, bare chip mounting is the ideal. However, for bare chips, quality control and handling are difficult. In answer to this, CSP (chip size package), or packages whose size is close to that of the chip, have been developed.
Of the forms of CSP semiconductor device developed, one form has a flexible substrate provided, patterned on the active surface of the semiconductor chip, and on this flexible substrate are formed a plurality of external electrodes. It is also known to inject a resin between the active surface of the semiconductor chip and the flexible substrate, in order to absorb the thermal stress.
However, in cases where resin alone is insufficient to absorb the thermal stress, another means is required.
The present invention has as its object the solution of the above described problems, and this object subsists in the provision of a semiconductor device and method of making the same, a circuit board, and an electronic instrument such that the package size is close to the chip size, and such that apart from the stress absorbing layer, thermal stress can be effectively absorbed.
DISCLOSURE OF INVENTION
The method of making a semiconductor device of the present invention comprises;
a step of providing a wafer on which are formed electrodes;
a step of providing a first stress relieving layer on the wafer avoiding at least a part of the electrodes;
a step of forming a first conducting portion over the first stress relieving layer from the electrodes;
a step of forming external electrodes connected to the first conducting portion on the first stress relieving layer;
and a step of cutting the wafer into individual pieces, and
wherein in at least one of the step of providing the first stress relieving layer and the step of forming the first conducting portion a construction is formed which increases the relief of stress.
According to the aspect of the present invention, since the conducting portions and external electrodes are formed over a stress relieving layer, this obviates the need for a substrate such as a patterned film with preformed external electrodes.
Besides, since the conducting portions between the electrodes and the external electrodes can be formed freely according to the requirements of the design, the layout of the external electrodes can be determined regardless of the layout of the electrodes. As a result, without changing the circuit design of the elements formed on the wafer, various semiconductor devices with the external electrodes in different positions can easily be fabricated.
Furthermore, according to the aspect of the present invention, after the stress relieving layer, conducting portions and external electrodes are formed on the wafer, the wafer is cut, to obtain individual semiconductor devices. As a result, the formation of the stress relieving layer, conducting portions and external electrodes on a large number of semiconductor devices can be carried out simultaneously, and the fabrication process can be simplified.
As the construction which increases the relief of stress, a depression may be formed on the surface of the first stress relieving layer, and the first conducting portion is formed to pass over the depression.
By this means, since the conducting portion is formed to be bent in a direction intersecting to the surface of the stress relieving layer, the stress can be absorbed by a variation of the bending condition, and wiring breaks can be prevented.
As the construction which increases the relief of stress, in the step of forming the first conducting portion, the first conducting portion may be formed so as to be bent in a direction of a horizontal plane on the first stress relieving layer.
There may further be a step of inserting an elastic body over the first conducting portion positioned at the depression. By means of this elastic body, stress can be further absorbed.
There may further be a step of providing a second stress relieving layer and a second conducting portion connected to the first conducting portion on the first stress relieving layer on which the first conducting portion is formed.
By this means, the stress relieving layer is formed as a plurality of layers, and the stress is thereby even more easily distributed.
At least one of the first conducting portion and the second conducting portion may be formed in planar form, to have its larger planar extent than its thickness.
By this means, since a signal is transmitted in the vicinity of a planar ground potential, an ideal transmission path is obtained.
A second stress relieving layer and a second conducting portion may be provided on the first stress relieving layer on which the first conducting portion is formed;
a third stress relieving layer and a third conducting portion may be provided on the second stress relieving layer on which the second conducting portion is formed; and
the second conducting portion may be formed in linear form, and the first and third conducting portions may be formed in planar form, to have their larger planar extent than that of the second conducting portion.
By this means, since the linearly formed second conducting portion is sandwiched between a pair of planar conducting portions, it is covered by surrounding wires at ground potential. In this way a construction similar to coaxial cable is obtained, and the signal passing through the second conducting portion is less susceptible to the influence of noise.
A pair of wires at ground potential may be formed parallel to and on both side of the first conducting portion.
By this means, since the linearly formed first conducting portion is sandwiched between a pair of wires, it is covered by surrounding wires at ground potential. In this way a construction similar to coaxial cable is obtained, and the signal is less susceptible to the influence of noise.
The semiconductor device of the present invention comprises:
a semiconductor chip having electrodes;
a first stress relieving layer provided on the semiconductor chip so as to avoid at least a part of the electrodes;
a first conducting portion formed from the electrodes over the first stress relieving layer; and
external electrodes formed on the first conducting portion positioned above the first stress relieving layer, and
wherein the first stress relieving layer is formed to have a depression on its surface, and the first conducting portion is formed to pass over the depression.
By this means, since the conducting portion is formed to be bent in a direction intersecting to the surface of the stress relieving layer, the stress can be absorbed by a variation of the bending condition, and wiring breaks can be prevented.
On the first conducting portion positioned over the depression, an elastic body may be provided so as to fill the depression.
The first conducting portion may be formed to be bent over the first stress relieving layer.
The first conducting portion may be formed to have a bellows form.
A second stress relieving layer and a second conducting portion connected to the first conducting portion may be provided on the first stress relieving layer on which the first conducting portion is formed.
By this means, the stress relieving layer is formed as a plurality of layers, and the stress is thereby even more easily distributed.
One of two conducting portions consisting of the first conducting portion and the second conducting portion may be formed in a linear form, and the other may be formed in planar form, to have its larger planar extent than that of the linear conducting portion.
The planar conducting portion may be at ground potential and a signal is input in the linear conducting portion.
The semiconductor device may further comprises;
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Oliff & Berridge PLC.
Seiko Epson Corporation
Williams Alexander O.
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