Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-06-11
2001-03-20
Lee, Eddie C. (Department: 2815)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S197000, C438S229000, C438S230000, C438S429000, C438S585000, C438S595000
Reexamination Certificate
active
06204148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor processing, and, more particularly, to a method of making a semiconductor device having a grown polysilicon layer that assists in transistor scaling.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor, e.g., channel length, junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size or scale of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Typically, the feature size of integrated circuit components (e.g., transistors) may be determined during the semiconductor manufacturing process using a variety of masking techniques, such as photolithography. Photolithography may be used to selectively isolate very small regions on the surface of a wafer. Generally, photolithography comprises coating the wafer with a photosensitive layer, such as a photoresist. The photoresist may then be selectively exposed to light through a master pattern on a photographic plate. The exposed portions of the photoresist may be developed and removed revealing selected areas of semiconductor material for further processing. In this manner, very fine integrated circuit components, such as the channel length of a field effect transistor, may be determined. Unfortunately, transistors and other semiconductor devices are desired with feature sizes smaller than photolithography and other masking techniques are capable of producing.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a partially formed semiconductor device including a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width.
Another aspect of the present invention is seen in a method for partially forming a semiconductor device. The method includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls. The first width of the opening is reduced to a second width by growing a layer of polysilicon adjacent at least a portion of the sidewalls of the opening.
REFERENCES:
patent: 5108945 (1992-04-01), Matthews
patent: 5963818 (1999-10-01), Kao et al.
patent: 6040214 (2000-03-01), Boyd et al.
patent: 0409681 A1 (1991-01-01), None
patent: 60-234375 (1985-11-01), None
Fulford H. Jim
Gardner Mark I.
Wristers Derick J.
Advanced Micro Devices , Inc.
Lee Eddie C.
Richards N. Drew
Williams Morgan & Amerson P.C.
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