Boots – shoes – and leggings
Patent
1996-05-06
1999-05-11
Elmore, Reba I.
Boots, shoes, and leggings
364700, 364707, 364 88, 364489, G06F17/10
Patent
active
059034815
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an integrated circuit for processing, for example, a digital image signal.
BACKGROUND ART
For example, in case of constructing a hardware for processing a digital image signal as a large scale integration (LSI), one of its methods is to develop and design an exclusive-use LSI corresponding to its process and another method is to use a DSP (Digital Signal Processor) having generality. The DSP comprises a product sum operator, an RAM/ROM, and the like and can execute digital signal processes of an FFT, a digital filter, and the like.
In case of the method of developing and designing the exclusive-use LSI, it is necessary to develop and design LSIs of the number corresponding to the number of kinds of digital signal processes. Although The DSP has excellency in generality, there is a problem of a bad efficiency.
DISCLOSURE OF INVENTION
It is, therefore, an object of the invention to provide an integrated circuit for processing a digital signal in which basic hardware constructions are made common and a plurality of functions can be realized by one chip.
According to the invention, there is provided an integrated circuit for processing a digital signal in which a plurality of circuit groups and selecting means which can switch at least two states are provided in a single integrated circuit and the selecting means is selectively controlled by a signal from the outside, characterized in that when the selecting means selects a first selection state, at least a part of the plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in the first connection state and, when the selecting means selects a second selection state, at least a part of the plurality of circuit groups is set to a second connection state different from the first connection state and is enabled to perform a second signal processing function different from the first signal processing function.
The selecting means is controlled by a control signal which is given from the outside of the integrated circuit, thereby switching the connection states of the plurality of circuit groups. The constructions of the hardwares in the integrated circuit are made common and the plurality of functions which can be selectively designated by a control signal can be realized by an integrated circuit of one chip.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a block diagram showing a construction of an embodiment of an integrated circuit according to the invention; FIG. 2 is a block diagram showing a construction of another embodiment of an integrated circuit according to the invention; FIG. 3 is a block diagram of an up-conversion circuit as one of functions which are realized by another embodiment of the invention; FIG. 4 is a schematic diagram for explaining an up-conversion process; FIG. 5 is a block diagram of an example of a delay and selecting circuit; FIGS. 6A and 6B are schematic diagrams which is used for explaining an example of the delay and selecting circuit; FIG. 7 is a block diagram of an example of a class sorting circuit; FIGS. 8A and 8B are schematic diagrams which is used for explaining an example of the class sorting circuit; FIG. 9 is a block diagram of an example of a construction for obtaining coefficients for the up-conversion process; FIG. 10 is a flowchart when a learning for obtaining prediction coefficients is executed by a software process; FIG. 11 is a block diagram of a noise reducer as another one of the functions which are realized by another embodiment of the invention; FIG. 12 is a block diagram of an example of a construction for obtaining coefficients for a noise eliminating process; and FIGS. 13A to 13D are schematic diagrams for explaining the noise eliminating process.
BEST MODE FOR CARRYING OUT THE INVENTION
The invention will be described hereinbelow with reference to the drawings. FIG. 1 shows a construction of an LSI 1 in an embodiment of the invention. Namely, in FIG. 1, a construction surrounded by a b
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Horishi Takashi
Kondo Tetsujiro
Elmore Reba I.
Frommer William S.
Marc McDieunel
Smid Dennis M.
Sony Corporation
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