System simulation for testing integrated circuit models

Details System simulation for testing integrated circuit models System simulation for testing integrated circuit models

1996-07-18

1999-05-11

Teska, Kevin J.

Boots, shoes, and leggings

364580, 364490, 39518309, 371 24, 371 251, G06F9/455;17/50

Patent

active

059034750

ABSTRACT:
Systems and methods of verifying the design of the ASIC during design and implementation phases are provided. The ASIC design is verified utilizing information from a system simulation in the customer's system environment. During system simulation, the invention captures "golden" vectors that may be used to test the ASIC during stand-alone simulation. The outputs generated by the ASIC during stand-alone simulation are compared to the outputs generated during the system simulation. Thus, the customer's system simulation is reproduced without having to reproduce the customer's system environment which allows the operation of the ASIC to be verified during various states of synthesis. Additionally, the test bench for testing the ASIC in stand-alone simulation is automatically generated eliminating the need for the user to manually generate a test bench.

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