Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2000-02-04
2001-06-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Read only systems
Semiconductive
C365S094000, C365S120000, C365S189070
Reexamination Certificate
active
06243284
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to multivalued mask read-only memories that are designed to store information of multiple bits in a single memory cell.
This application is based on Patent Application No. Hei 11-30680 and Patent Application No. Hei 11-96765 both filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In general, technology of multivalued cells each storing information of multiple bits is known to actualize large capacities for read-only memories (or ROMs). Japanese Patent Application, First Publication No. Hei 8-297982 discloses an example of a multivalued mask ROM, in which codes are written to a ROM in manufacture by changing thresholds (Vt) of cell transistors.
FIG. 9
is a circuit diagram showing a part of a cell array used for the aforementioned multivalued mask ROM. Herein, thresholds Vt
0
, Vt
1
, Vt
2
, Vt
3
are respectively set to transistors M
00
, M
10
, M
01
, M
11
, wherein those thresholds differ from each other in accordance with a relationship of Vt
0
<Vt
1
<Vt
2
<Vt
3
. For example, a word line WL
0
is selected and is changed in electric potential by three steps as shown
FIG. 10
from zero level to a prescribed level. Thus, it is possible to read out 2-bit information from the transistor M
00
or M
01
.
In order to change ROM codes of the multivalued mask ROM in manufacture, the thresholds Vt are changed by changing channel ion implantation to the cell transistors.
However, the aforementioned technique suffers from problems, as follows:
A first problem is caused by formation of ROM codes, which are formed by the channel ion implantation before formation of gates. At revision of the ROM codes, it is necessary to change masks in lower layers of integrated circuits. Such changes variously influence post-processes in manufacture of the integrated circuits, so it takes a great number of days in designing the masks and in manufacturing the integrated circuits. For this reason, it takes a longer turnaround time (or TAT) for revision.
A second problem is that the revision of the ROM codes needs a great number of modified masks. In case of a four-valued (or 2-bit) mask ROM, for example, it is necessary to modify at least two masks.
In a method in which ROM codes are written in response to magnitude of the thresholds Vt, it is necessary to change impurity density with respect to each of the cell transistors. In the case of the four-valued mask ROM, it is necessary to perform ion implantation two times, that is, it is necessary to perform ion implantation corresponding to Vt
1
and ion implantation corresponding to Vt
2
respectively. Herein, an amount of the ion implantation corresponding to Vt
2
is greater than an amount of the ion implantation corresponding to Vt
1
.
Specifically, first ion implantation corresponding to Vt
1
is performed with respect to the cell transistors corresponding to Vt
1
, Vt
3
by using a first mask, and second ion implantation corresponding to Vt
2
is performed with respect to the cell transistors corresponding to Vt
2
, Vt
3
by using a second mask.
As described above, the ion implantation is performed two times on the cell transistor corresponding to Vt
3
, which has a largest amount of ion implantation and a highest impurity density. In addition, ion implantation is not performed on the cell transistor corresponding to Vt
0
, which has a lowest impurity density. Thus, using two masks, it is possible to establish a relationship in impurity density in which Vt
0
<Vt
1
<Vt
2
<Vt
3
.
A third problem is a limitation of integration of the integrated circuits due to an alignment accuracy of ion implantation and spread diffusion of impurities. This is because heat treatment corresponding to the post-process of the ion implantation broadens impurities-diffused regions so that it is impossible to reduce gate pitches so much.
In order to form cell transistors, having different thresholds, to adjoin each other in a same active region, the known CMOS process (where “CMOS” is an abbreviation for “Complementary Metal-Oxide Semiconductor”) in mass production provides a gate length of 0.25 &mgr;m with a minimum gate pitch of 0.5 &mgr;m or so. Such a minimum gate pitch is determined by the alignment accuracy of the ion implantation and the spread diffusion of impurities. For this reason, it will not be reduced so much even if fine manufacture of the CMOS process is developed.
A fourth problem is complication in potential control of the word line(s) to read out codes stored in cells. That is, the aforementioned method that changes thresholds uses a number of different thresholds, which is identical to a number of states being stored in one cell. To discriminate them, it is necessary to control the word line to be at each of different potential levels, a number of which is smaller than the number of states being stored in one cell by “1”. In the case of the four-valued mask ROM, it is necessary to control the word line to be at each of “three” potential levels as shown in FIG.
10
.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a multivalued mask ROM which is reduced in turnaround time for revision of ROM codes and which is also reduced in a number of modified masks being required for revision of ROM codes.
It is another object of the invention to provide a multivalued mask ROM, integration of which is improved.
It is a further object of the invention to provide a multivalued mask ROM, in which potential control can be made on word lines in a simple manner.
A multivalued mask ROM is configured by arranging cell transistors in a matrix form, which is defined by wiring word lines and ground lines in rows and by wiring bit lines in columns. Each of the cell transistors is encompassed by a word line, a ground line and at least two bit lines. Herein, gates of the cell transistors which align in a same row are connected with a same word line, while sources and drains of the cell transistors are adequately connected or disconnected with the ground line and bit lines. In an integrated circuit, contacts are formed between n+ regions, first-layer metal and second-layer metal on a well region to establish connections by which the source and drain of the cell transistor are adequately connected with the ground line and/or bit lines. That is, ROM codes are formed using the contacts.
A circuitry is provided for the multivalued mask ROM to read out stored information of the cell transistors in synchronization with a clock signal. In Low-level duration of the clock signal, the circuitry performs precharge to a first bit line and pull-down to a second bit line. In High-level duration of the clock signal, the circuitry stops the precharge to the first bit line and the pull-down to the second bit line. In addition, the circuitry activates the word line to detect levels of the first and second lines, which are used as values for a two-bit code corresponding to stored information of the cell transistor. For example, a two-bit code (00) is determined as stored information of the cell transistor whose source and drain are not at all connected with the ground line and bit lines. In addition, a two-bit code (11) is determined as stored information of the cell transistor whose source and drain are respectively connected with the first and second bit lines.
Thus, it is possible to reduce TAT in manufacture for revision of the ROM codes, which are formed using the contacts. In addition, all the cell transistors have a single threshold, so it is unnecessary to perform ion implantation for changing thresholds. That is, it is possible to improve integration of the cell transistors in the multivalued mask ROM. Further, it is possible to perform potential control on the word lines in a simple manner because only two levels (e.g., High level and Low level) are required to control the word lines in potential.
REFERENCES:
patent: 5556800 (1996-09-01), Takizawa et al.
patent: 5650959 (1997-07-01), Hayashi et al.
patent: 568034
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
Le Thong
NEC Corporation
Nelms David
LandOfFree
Multivalued mask read-only memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multivalued mask read-only memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multivalued mask read-only memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2504579