Booster including charge pumping circuit with its electric...

Details Booster including charge pumping circuit with its electric... Booster including charge pumping circuit with its electric...

2000-02-11

2001-06-19

Wong, Peter S. (Department: 2838)

Electric power conversion systems

Current conversion

With voltage multiplication means

C363S059000, C307S110000

Reexamination Certificate

active

06249445

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a booster including a charge pumping circuit. More particularly, the present invention is related to a booster which includes a charge pumping circuit and can reduce its electric power consumption.
2. Description of the Related Art
A booster including a charge pumping circuit is widely used in semiconductor apparatuses. A conventional booster is disclosed in Japan Laid Open Patent Application (JP-A-Heisei, 1-241659). The conventional booster has a switching circuit as shown in FIG.
1
. The switching circuit
201
generates a clock signal CIN from a standard clock signal CLK, and sends it through a clock driver
202
to a charge pumping circuit
203
. A frequency of the clock signal CIN is switched on the basis of whether the semiconductor apparatus including the booster is in a standby mode or a normal operation mode. The charge pumping circuit
203
boosts a voltage V
IN
inputted from an input terminal. The charge pumping circuit
203
generates a voltage V
OUT
higher than the voltage V
IN
and further outputs the voltage V
IN
from an output terminal. The clock signal CIN is used to boost the voltage V
IN
to the voltage V
OUT
.
The switching circuit
201
has a 1
divider
204
and a selector
205
, as shown in FIG.
2
. The 1
divider
204
is provided with dividers
206
to
209
. The selector
205
is provided with an inverter
210
, AND gates
211
,
212
and an OR gate
213
.
The switching circuit
201
operates differently depending on whether the semiconductor apparatus is in the normal operation mode or the standby mode. At a time of the normal operation mode, the switching circuit
201
outputs the standard clock signal CLK as the clock signal CIN. At a time of the standby mode, the switching circuit
201
outputs a clock signal in which a standard clock signal is divided by 1
at the time of the standby mode, as the clock signal CIN.
Incidentally, other boosters are disclosed in Japan Laid Open Patent Application (JP-A-Showa 64-39263, JP-A-Heisei 5-64429, JP-A-Heisei 7-160215, JP-A-Heisei 7-226078, JP-A-Heisei 10-304653 and JP-A-Heisei 10-304654).
The conventional booster consumes large electric power at the time of the normal operation. This is because the conventional booster always sends a signal having the same frequency as the standard clock signal CLK to the charge pumping circuit, as the clock signal CIN at the time of the normal operation. A booster is desired in which the electric power consumption is reduced at the time of the normal operation.
Also, the conventional booster is large in variation of an output voltage. This is because the output voltage is not controlled. A booster is desired in which the variation of the output voltage is small.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a booster in which the electric power consumption can be reduced at the time of the normal operation. Another object of the present invention is to provide a booster in which the variation of an output voltage is small. Still another object of the present invention is to provide a booster in which when the output voltage is largely deviated from a target value, it can be quickly recovered.
In order to achieve an aspect of the present invention, a booster includes a switching circuit outputting a clock signal and a charge pumping circuit boosting an input voltage to generate an output voltage in response to the clock signal. The switching circuit selects one from among a plurality of frequencies as a frequency of the clock signal in response to the output voltage.
The frequency of the clock signal may be set to the highest one of the plurality of frequencies when an integrated circuit including the booster is reset.
The frequency of the clock signal may be set to the highest one of the plurality of frequencies when a power supply of an integrated circuit including the booster is turned on.
The frequency of the clock signal may be set to the lowest one of the plurality of frequencies when an integrated circuit including the booster is in a standby mode.
The frequency of the clock signal may be selected in response to difference between the output voltage and a reference voltage.
In that case, the frequency of the clock signal is desirably increased when the output voltage is decreased.
The switching circuit may include a voltage comparator, a frequency selector and a outputting unit. The voltage comparator compares the output voltage with a reference voltage and generates a first signal indicating whether or not the output voltage is higher than the reference voltage. The frequency selector selects one of the plurality of frequencies in response to the first signal and generates a second signal indicating which of the plurality of frequencies is selected. The outputting unit outputs the clock signal having the one of the plurality of frequencies in response to the second signal.
In order to achieve another aspect of the present invention, a method of operating a booster with a charge pumping circuit is composed of selecting one from among a plurality of frequencies as a frequency of a clock signal, generating the clock signal having the frequency, and boosting an input voltage to generate an output voltage in response to the clock signal. The selecting is performed in response to the output voltage.
The selecting may include selecting the highest one of the plurality of frequencies as the frequency of the clock signal when an integrated circuit including the booster is reset.
The selecting may include selecting the highest one of the plurality of frequencies as the frequency of the clock signal when a power supply of an integrated circuit including the booster is turned on.
The selecting may include selecting lowest one of the plurality of frequencies as the frequency of the clock signal when an integrated circuit including the booster is in a standby mode.
The selecting is performed in response to difference between the output voltage and the reference voltage.
The frequency of the clock signal is increased when the output voltage is decreased.


REFERENCES:
patent: 4141064 (1979-02-01), Nagashima
patent: 5159543 (1992-10-01), Yamawaki
patent: 5414614 (1995-05-01), Fette et al.
patent: 5499183 (1996-03-01), Kobatake
patent: 5635776 (1997-06-01), Imi
patent: 5959853 (1999-09-01), Kos
patent: 6020781 (2000-02-01), Fujioka
patent: 6026002 (2000-02-01), Viehmann
patent: 64-39263 (1989-02-01), None
patent: 1-241659 (1989-09-01), None
patent: 5-64429 (1993-03-01), None
patent: 7-160215 (1995-06-01), None
patent: 7-226078 (1995-08-01), None
patent: 10-304653 (1998-11-01), None
patent: 10-304654 (1998-11-01), None

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