Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-04-30
2001-03-20
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S757020
Reexamination Certificate
active
06204678
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and more particularly to an improved interconnect for testing semiconductor dice and wafers. The invention also relates to a test method and system that employ the interconnect.
BACKGROUND OF THE INVENTION
For testing semiconductor dice, temporary electrical connections must be made to the integrated circuits on the dice. Typically, the electrical connections are made through contact locations, such as bond pads or test pads, formed on the faces of the dice. Testing at the wafer level can be performed using probe cards and a wafer probe handler. Probe cards include probe needles that electrically contact the contact locations on the wafer. Test circuitry associated with the wafer probe handler applies test signals through the probe card to the integrated circuits.
Testing can also be performed on dice that have been singulated from the wafer. In this case, temporary packages are adapted to house a single bare die on a burn-in board or other test apparatus. The temporary packages typically include an interconnect having contact members configured to electrically contact the contact locations on the die.
With wafer level testing, electrical connections must be made to the probe card. With die level testing, electrical connections must be made to the interconnect for the temporary package. These electrical connections are typically bonded connections. With bonded connections it can be difficult to separate a probe card from the wafer handler, or an interconnect from a temporary package, without damage. This makes replacing and interchanging the probe cards and interconnects difficult.
Another requirement of the connections to a probe card or interconnect is that the electrical connections must sometimes be capable of transmitting signals at high test speeds (e.g., 500 MHz). It is desirable to transmit test signals without generating parasitic inductance and cross coupling (i.e., “cross talk”).
Often times the electrical connections with the probe card or interconnect are sources of parasitic inductance. For example, with temporary packages having wire bonded interconnects, it can be difficult to accurately space the bond wires from one another. Accordingly, capacitive coupling can occur between adjacent bond wires generating noise and spurious signals.
The problems of parasitic inductance and cross coupling can be compounded by the large number of bond pads contained on later generations of semiconductor dice. In particular, a large number of bond pads requires a corresponding number of electrical connections to the probe card or interconnect. It can be difficult to make these electrical connections without forming parasitic inductors and initiating cross talk and interconductor noise.
The present invention is directed to an improved interconnect capable of high speed testing of either wafers or singulated dice, with reduced parasitics inductance. In addition, non-bonded electrical connections can be made to the interconnect, such that removing and replacing the interconnect is facilitated.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having contact members configured to make temporary electrical connections with contact locations on the dice. The contact members can be configured to electrically contact bumped contact locations on the dice, such as solder bumps, or flat contact locations on the dice, such as metal bond pads.
The interconnect also includes patterns of conductors in electrical communication with the contact members. In addition, contact receiving cavities are formed on the substrate to facilitate an electrical connection from a testing apparatus to the conductors. Each separate conductor is configured to connect to a mating electrical connector of the testing apparatus, such as a spring clip, socket contact, spring loaded pin, or other member. The contact receiving cavities permit non-bonded, direct electrical connections to be made from testing circuitry to the interconnect.
The interconnect substrate can be formed of silicon, or an electrically insulating material, such as ceramic. For dice with bumped contact locations, the contact members can comprise depressions formed in the substrate and covered with a conductive layer. The depressions can be formed at the same time as the contact receiving cavities using a bulk micro-machining process. Alternately, for dice with flat contact locations, the contact members can include penetrating projections covered with a conductive layer.
The interconnect can be configured for use with a die level test system or a wafer level test system. With a die level test system, the interconnect can be mounted within a temporary package for a single die. The temporary package is adapted for use with a testing apparatus, such as a burn-in board, in electrical communication with testing circuitry. The temporary package can include a base and a force applying mechanism for biasing the die and interconnect together. In the die level test system, the interconnect establishes temporary electrical communication with the contact locations on the die, and provides conductive paths to and from the testing circuitry to the contact locations.
With a wafer level test system, the interconnect can be configured to contact semiconductor dice contained on a wafer. A conventional testing apparatus, such as a wafer probe handler, can be used to support the interconnect and the wafer. For mounting the interconnect to the testing apparatus, a conventional probe card fixture can be modified for use with the interconnect. The probe card fixture can include an opening for receiving the interconnect. In addition, electrical connectors can be formed on the probe card fixture, along a periphery of the opening, for physically supporting, aligning and electrically connecting the interconnect. In this embodiment, the electrical connectors on the probe card fixture engage the contact receiving cavities on the interconnect. In addition, a biasing member can be used to cushion forces applied by the testing apparatus to the interconnect, and to allow the contact members to self planarize to the contact locations on the wafer. The biasing member can be formed of a compressible elastomer or as a metal filled elastomer configured to dissipate heat.
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patent: 5844418 (199
Akram Salman
Farnworth Warren M.
Wark James M.
Gratton Stephen A.
Metjahic Safet
Micro)n Technology, Inc.
Solis Jose M.
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