Use of biased high threshold voltage transistor to eliminate...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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C327S537000, C327S544000

Reexamination Certificate

active

06225852

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit design. More particularly, the present invention relates to circuit design techniques to ensure high-speed, low-power operation at reduced supply voltages in semiconductor memory devices.
In the design of integrated circuits, there is a trend to power the integrated circuits using decreasing supply voltage levels. Previous circuit families operated at 5 volts and 3 volts. Current families operate at 1.8 volts and future families will operate at 1.0 volts nominal supply voltage. Under worst case conditions, the supply voltage may be as low as 0.9 volts. These lower supply voltages create design and operation problems.
One problem is encountered when adapting conventional complementary metal-oxide-semiconductor (CMOS) circuits for low voltage operation. Conventional n-channel and p-channel transistors have threshold voltages (also called turn-on voltages) too large for satisfactory operation in low voltage applications. For example, a conventional p-channel transistor has a threshold voltage of approximately −1.2 volts and a conventional n-channel transistor has a threshold voltage of approximately 1.1 volts. In a 1.0-volt supply device, these conventional transistors will never be turned fully on to sink or source current to a load.
One solution is lowering the threshold voltage of the transistors. With the magnitude of the p-channel and n-channel threshold voltages set at −0.4 volts and 0.6 volts, respectively, the transistors can turn on fully even at worst case supply voltages. This is important to device performance, since the drain current IDS is proportional to the square of the difference between the drain to source voltage VDS and the threshold voltage Vt. However, transistors with low threshold voltages tend to have higher subthreshold current leakage. In a large integrated circuit with thousands or millions of transistors, the total standby current would be too large for practical applications. The large standby current would increase overall power consumption for the device to unacceptable levels.
Accordingly there is a need for an improved method and apparatus for reducing standby current in an integrated circuit, particularly an integrated circuit employing reduced-threshold voltage transistors in a low supply voltage application.
BRIEF SUMMARY
By way of introduction only, an integrated circuit in accordance with the present invention disconnects Vss or ground potential from the operating circuitry of the integrated circuit in the standby mode. Vss is received from off-chip and is supplied to the entire chip through a very large reduced-threshold voltage transistor. In the active mode, the well of the transistor is boosted by a predetermined voltage to lower the threshold voltage of the transistor for operation at low Vcc. In the standby mode, the gate and well of the transistor are grounded to the off-chip Vss, turning off the transistor and letting voltage of the operating circuitry float. This allows very quick turn on from standby to the active mode.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.


REFERENCES:
patent: 4460835 (1984-07-01), Masuoka
patent: 5644266 (1997-07-01), Chen et al.
patent: 5986443 (1999-11-01), Jeong
patent: 6040610 (2000-03-01), Noguchi et al.
patent: 6061267 (2000-05-01), Houston
B.Streetman, Solid State Electronic Devices, Third Edition, 1990, section 8.3.7, pp. 320-322.

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