Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
1998-08-28
2001-05-22
Pan, Daniel H. (Department: 2171)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S023000, C712S244000, C712S214000, C711S202000
Reexamination Certificate
active
06237076
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to an improved data processing system, and in particular to a method and system working with mixed instruction sets, e.g. 32 bit and 64 bit instructions within the data processing system. Still more particularly, the present invention relates to a method and system for renaming registers of said system as they are required for the concurrent execution of 32 bit and 64 bit instructions while having data dependencies among each other.
2. Description of the Related Art
As the quest for greater data processing system performance continues, central processing unit (CPU) designers have implemented superscalar data processing systems that are capable of issuing multiple independent instructions into multiple execution pipelines, wherein multiple instructions are executed in parallel. An example of such a superscalar data processing system is the superscalar microprocessor sold under the trademark “PowerPC” by IBM Microelectronics and Motorola Semiconductor. The “PowerPC” architecture is described in more detail in various user's manuals, including ‘PowerPC 603-RISC MICROPROCESSOR USER'S MANUAL,” copyright 1994, IBM Part No. MPR6O3UMU-01.
Within the superscalar microprocessor, instructions are fetched from an instruction cache and are dispatched in program order to one of a plurality of execution units, wherein the instruction is executed by an execution unit appropriate for the particular type of instruction. For example, floating-point instructions are dispatched to one or more floating-point execution units, while fixed-point instructions are dispatched to one or more integer units. While instructions are dispatched in program order, instruction execution may occur out of order, depending upon availability of execution units and other data processing system resources.
In the superscalar processor, instructions may be dispatched, executed, and “finished” before other instructions that were previously dispatched. In order to prevent out-of-order instruction execution from placing data in an architected register at the wrong time, instruction execution is “completed” in program order by a completion unit. Thus, a subsequently dispatched instruction may “finish” before a previously dispatched instruction finishes, but the subsequently dispatched instruction may not be “completed” before completion of the previously dispatched instruction.
As is known in the art, “PowerPC” includes register renaming techniques for resolving data dependencies between instructions following each other after passing the dispatching unit. Logical registers are assigned to a plurality of physical registers in an assignment list so that they can be passed to a plurality of reservation stations each dedicated to supply a given execution unit with instructions to be executed.
With increasing need to address more than 4 Gigabyte of data—the maximum address space being addressable with 32 bit—the address calculation necessitates registers and arithmetic units capable to process address data with the next step size of 64 bit addresses. A special need exists, however, to handle both, 32 bit and 64 bit handling in structions—mixed instruction sets—in one program.
In general, 32 bit instructions leave the high part of a 64 bit register unchanged, succeeding 64 bit instructions use the full register size with the changes made by 32 bit instructions.
Register renaming as used for speculative instruction execution requires to write newly generated result data into a new physical register, thus ensuring that architected, logical registers can be kept in program order at retire time and to have a mean to discard faulty executed instructions.
The result data of the preceding 32 bit instructions cannot be used, because consecutive 32 bit LOAD instructions would get a source dependency on the preceding LOAD instruction. All 32 bit LOAD instructions would be executed in-order: each LOAD had to wait until the preceding one has processed its result data, required as source of the high part register contents in the succeeding instruction.
Straight forward 64 bit/32 bit register renaming would break a 64b register into a high and a low part register and would rename the both registers separately. But this approach would double the renaming logic with possible impact on the cycle time of the processor.
SUMMARY AND OBJECTS OF THE INVENTION
One object of the invention is to allow 32 bit LOAD instructions to be executed out-of-order and in parallel on different load units even when there are data dependencies to a preceding 64 bit instruction whenever the high part of a 64b register is available.
Another object of the invention is to implement the proposed method for mixed instruction sets of 32 bit and 64 bit instruction sets, respectively with a minimum expense of logic circuits.
These and other objects are achieved in a data processing system by a method and a system for renaming registers in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program.
In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (
28
).
The basic idea is to copy the high part of the 64 bit register, which was changed by a preceding 64 bit instruction to the new allocated target register of a 32 bit instruction. The copy process is made in parallel to the execution of the 32 bit instruction, with no performance penalty. In case of a 32 bit LOAD instruction the source register address is taken from the so-called 64 bit-GPR file (general purpose file), which is addressed by the physical register number used as target register of the preceding 64 bit instruction. For 32 bit ALU instruction the first operand specifies source and target of the ALU operation; therefore the high part of the first source operand contains already the correct copy data.
Thus, new allocated registers, which are used to hold the result data for a 32 bit instruction in the low part of the register must be loaded with the high part data of the preceding 64 bit instruction if the same logical register is specified.
The proposed renaming method has no impact on the number of rename registers and register contents valid logic i.e. complex logic macros such as the reservation station remain unchanged.
The above, as well as additional objects, features, and advantages of the present invention, will become apparent in the following detailed written description.
REFERENCES:
patent: 5454091 (1995-09-01), Sites et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5574928 (1996-11-01), White et al.
patent: 5966530 (1999-10-01), Shen et al.
patent: 5978887 (1999-11-01), Yeager
Gaertner Ute
Getzlaff Klaus Jorg
Laub Oliver
Pfeffer Erwin
Augspurger Lynn L.
Chen Te Yu
International Business Machines - Corporation
Pan Daniel H.
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