Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1997-09-16
2001-06-19
Britton, Howard (Department: 2713)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C348S699000
Reexamination Certificate
active
06249550
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to an apparatus and a method for estimating a motion vector utilized to compensate for motion of an image in a prediction coding process of a moving picture.
2. Description of the Related Art
In a conventional method and apparatus for estimating a motion vector estimating method, a current picture to which a prediction coding process is performed is divided into a plurality of blocks, for example, to have 16 pixels in a horizontal direction and 16 pixels in a vertical direction. These blocks are referred to as current blocks. A search region is predetermined in a reference picture for each of the above-described current blocks to have as a center of the search region the positions corresponding to the horizontal position and the vertical position of a pixel position of each current block. The predetermined search region in the reference picture is referred to as a search window. A block matching process is carried out between a specific one of the current blocks and the search window corresponding to the specific current block to estimate a position on which a predetermined evaluation function has the minimum value for obtaining a motion vector. The conventional motion vector estimating apparatus is directed to a purpose that the motion vector can be more correctly obtained.
A first conventional example of a motion vector estimating apparatus is disclosed in, for example, Japanese Laid Open Patent Application (JP-A-Showa 61-201583). In the reference, a limit value is provided to limit a reference region used to search the motion vector in accordance with a change amount of a motion vector detected in a previous frame to a current frame. When the motion vector change amount exceeds the limit value, this limit value is outputted.
Also, a second conventional example of the motion vector estimating apparatus is proposed in Japanese Laid Open Patent Application (JP-A-Heisei 5-328333), in which several search windows or regions for a motion vector are prepared to be different from each other in position. One of the several reference windows or regions is selected in accordance with the change amounts of the motion vectors detected in a previous frame to the current frame.
Further, a third conventional example of the motion vector estimating apparatus is proposed in Japanese Laid Open Patent Application (JP-A-Heisei 7-203457), in which an accumulating process of absolute values of differences is executed in a parallel manner in the block matching process. As a result, the capacity of a buffer for signals used in the accumulation is reduced so as to increase the processing speed.
Furthermore, a fourth conventional example of the motion vector estimating apparatus is proposed in Japanese Laid Open Patent Application (JP-A-Heisei 7-250328), in which motion vectors used to compensate for the moving image prediction are estimated in accordance with a plurality of prediction modes with a small hardware amount.
There are the following problems in the above-described conventional examples of the motion vector estimating techniques.
(1) The first problem is in the following point. That is, power consumption cannot be reduced in the first conventional example of the motion vector estimating apparatus in which the limit value is provided to limit the search region for the motion vector. This is because in the motion vector estimating apparatus described in Japanese Laid Open Patent Application (JP-A-Showa 61-201583), the limit value is only introduced to the reference region. The calculation time and the calculation amount for the block matching process to be executed cannot be reduced in actual. In other words, since the calculation time and the calculation amount cannot be reduced, the power consumption of the motion vector estimating apparatus cannot be reduced.
In the block matching process as described in, for instance, Japanese Laid Open Patent Application (JP-A-Heisei 7-203457) and Japanese Laid Open Patent Application (JP-A-Heisei 7-250328), the operation time is reduced by employing parallel processing. However, the reason why the operation time cannot be reduced is that if the limit value is provided as in the motion vector estimating apparatus described in Japanese Laid Open Patent Application (JP-A-Showa 61-201583), the parallel degree of the above-described parallel processing decreases. As a result, the operation time cannot be reduced.
(2) The second problem is in that the correct motion vector cannot be obtained in the conventional motion vector estimating apparatus as proposed in Japanese Laid Open Patent Application (JP-A-Heisei 5-328333), in which the several reference regions for the motion vector are prepared. This is because in the method for selecting the optimum reference region from the prepared reference regions, when pictures are such complex that more than one object move, the object moving direction cannot be exclusively determined. As a result, the optimum reference region cannot be selected from the prepared several reference regions.
Also, in the above-described motion vector estimating apparatus described in Japanese Laid Open Patent Application (JP-A-Heisei 5-328333), if the size and/or shape of the reference region cannot be previously determined, then the parallel degree of the apparatus for executing the block matching process would be lowered. As a consequence, since the shape of the reference region is limited and thus the proper reference region cannot be utilized, the correct motion vector cannot be obtained.
(3) The third problem is in that in the motion vector estimating apparatus proposed in Japanese Laid Open Patent Application (JP-A-Heisei 7-203457), the difference absolute value accumulating process is carried out in the parallel manner using the small buffer for signals for the calculation. However, in the motion vector estimating apparatus, the hardware amount of the block matching circuit for executing the difference absolute value accumulating process in the parallel manner increases so that the chip area for the block matching circuit is increased as well as the power consumption is increased. This is because in the motion vector estimating apparatus as described in Japanese Laid Open Patent Application (JP-A-Heisei 7-203457) and Japanese Laid Open Paten Application (JP-A-Heisei 7-250328), a large amount of wiring lines must be provided for a processing element as the minimum unit of the block matching circuit. Thus, the valid data can be continuously entered into the respective processing elements such that the parallel degree is increased. As a consequence, a chip area required for the wiring lines increases considerably.
Also, in the above-explained motion vector estimating apparatus described in Japanese Laid Open Patent Application (JP-A-Heisei 7-203457) and Japanese Laid Open Patent Application (JP-A-Heisei 7-250328), there is another problem. That is, the minimum value determining unit determines the minimum value of a summation of absolute values of differences accumulated values in the respective processing elements, and the chip area required for wiring lines is considerably increased, because a total number of wiring lines is very large which are used to be connected from the minimum value determining unit.
(4) The fourth problem is in that if the size and/or shape of the reference region is allowed to be varied in the motion vector estimating apparatus in which the difference absolute value accumulating process is executed in the parallel manner, the hardware amount of the block matching circuit for executing the difference absolute value accumulation process in the parallel manner is increased. As a result, the chip area increases and also the power consumption increases. Also, at this time, the parallel degree is reduced. This is because the large amount of wiring lines must be provided to continuously enter the valid data into the processing elements as the minimum unit for constituting the block matching circuit.
Also, it is because the data
Mizuno Masayuki
Ooi Yasushi
Britton Howard
Diep Nhon T
Foley & Lardner
NEC Corporation
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