Semiconductor device manufacturing: process – Including control responsive to sensed condition
Reexamination Certificate
1997-11-28
2001-01-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
C438S014000
Reexamination Certificate
active
06174738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. More specifically, this invention relates to the determination of disposition criteria utilized in the determination of whether a particular lot is to be advanced to the next process. Even more specifically, this invention relates to the determination of disposition criteria utilized in the determination of whether a particular lot is to be advanced to the next process using a critical area cost disposition feedback system.
2. Discussion of the Related Art
Production costs for manufacturing state-of-the-art semiconductor wafers are increasing rapidly, devices are becoming larger and more dense, process technologies are becoming more complex with cycle times extending, and selling prices for the end products are extremely volatile. Due to the complex interaction of these and other variables, the decision making process for discrepant material in-line is becoming increasingly difficult. Presently there is no methodology for a decision to be made based upon an analytical rational basis.
The manufacturing of semiconductor wafers takes place in “lots” of wafers. A lot may include any selected number of wafers. Because it is virtually impossible to test each and every wafer in a lot, one or more wafers are selected as representative of the condition of the lot. For example, if a selected wafer indicates that the yield for the lot may be lower than a required minimum yield, the entire lot is placed on hold. The cause of the low yield can be determined, a remedial action may be taken, or the entire lot may be scrapped. As can be appreciated, the scrapping of a lot or lots of semiconductor wafers is very expensive and may be the difference between a profitable year and a disastrous year. When the selected wafer indicates that the yield will be extremely low or non-existent, the decision is simple. However, can there be a case when a defect density determination for a particular layer indicates that the yield will be 70%, 80% or even 95% or higher for that process step and a decision to continue processing the lot may be unprofitable. The answer, of course, depends partly upon which process step is involved and whether the particular process step is one in which an expected low yield for that step is unavoidable and the preceding and remaining process steps have high yields to compensate for the low yield. The criticality of minute changes in yields for a particular process step can be illustrated as follows. If there are 100 process steps and yield determinations are made at 50 of the process steps and show that at each process step there is yield of 99%, this would indicate that an overall yield of approximately 60% (calculated as follows: 0.9950) would be achieved. On the other hand, if it is determined that there is only a yield of 95% for each layer, the overall yield would only be approximately 8%. This is a very simple illustration and indicates the extreme criticality of determining not only the yield of the particular layer, but realizing the effect of a yield determination on the overall yield. The person making the decision whether to move the lot to the next process step should have current data including the cost of each succeeding process step and the selling price of the end product. As can be appreciated, a yield of 30% for some products is an acceptable yield and results in a profitable process whereas for other parts, a yield of 80% may just be the breakeven point. An incorrect decision, either to continue processing the lot resulting in an unprofitable run or to scrap a lot that would have been profitable, can result in lost profits for the manufacturing company.
Tools currently exist that monitor the defect density of a wafer at a particular process step and tools exist, or are being created, that predict device yield based upon a concept called “critical area.” The current concept of “critical area” is defect size and layer layout dependent. The critical area provides an estimate of killer propensity for killer type defects found within the layout area such that a killer defect found within the layout area will have a certain aptitude to disrupt the pattern to make the part non-functional. However, the current concept of critical area does not include a feedback system to consider the cost of each process step and the current selling price of the completed product.
Therefore, what is needed is a tool that is able to gather together all the necessary up-to-date information, including cost information, and provide a disposition based on available current and past data concerning a wafer lot on hold.
SUMMARY OF THE INVENTION
A Critical Area Cost Disposition Feedback System in accordance with the present invention solves the above and other problems associated with the current decision making process concerning the disposition of discrepant wafer lots placed on hold in a wafer manufacturing process.
The above and other objects and advantages of the present invention are attained through a system that provides the capability to gather information from diverse sources. Such sources include a wafer layout tool (such as a CAD tool), a wafer lever parametrics database (such as WORKSTREAM), a defect server (such as a Defect Management System tool). The system of the present invention manipulates the collected data to provide information to the decision making process whether or not a wafer lot on hold because of a particular defect density should be scrapped or released at the current location.
The present invention is attained through a system of determining an accurate disposition decision for each inspected layer in a wafer lot wherein a measured defect density is compared to a calculated disposition criterion determined for each inspected layer. If the measured defect density is above the calculated disposition criterion the wafer lot is placed on hold and if the measured defect density is at or below the calculated disposition criterion the wafer lot is sent to the next process. The disposition criterion for each layer is determined from a yield value determined for each layer. The yield value is the yield necessary for each layer to obtain a profitable product and is determined from cost data for each die in the wafer lot and a risk factor determined by management and includes market data such as selling price and demand for the product. The yield value is combined with defect sensitivity determined for each layer. The defect sensitivity is determined from the combination of critical area and historical frequency for each layer.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
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Gary Griffith Quality Technician's Handbook J. Wiley and Sons pp. 346, 348, 1986.
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Chen Ming Chun
Steffan Paul J.
Advanced Micro Devices , Inc.
Blum David S
Bowers Charles
Nelson H. Donald
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