Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-04-29
2001-03-06
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S754000
Reexamination Certificate
active
06198167
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor structures that exhibit reduced contact resistance and especially those structures containing polycrystalline silicon interconnection plug or stud to an epitaxial monocrystalline silicon substrate. In addition, the present invention is concerned with a method for fabricating a semiconductor structure which exhibits reduced contact resistance.
BACKGROUND OF INVENTION
Polycrystalline silicon and particularly in-situ doped polycrystalline silicon has been suggested as a contact material especially for ultralarge scale integration technology. Doped polycrystalline silicon has been suggested as a suitable plug or stud material (for a contact-hole or via) that makes contact with an underlying epitaxial monocrystalline silicon substrate. The silicon can be co-deposited on the desired substrate along with the dopant by chemical vapor deposition process. It has been reported that relatively deep-submicron contact holes have been successfully plugged with polysilicon.
Continuing efforts have been underway for providing improved methods for depositing doped polycrystalline silicon especially for improving the deposition rates and controlling radial non-uniformity across the wafer that has been caused by adding the dopant gas. Notwithstanding the strides that have been made, room still exists for improvement. This is especially so with respect to attempting to further reduce the contact resistance.
For instance, in-situ phosphorus-doped polycrystalline silicon exhibits contact resistance of about two-three times lower than a polycrystalline silicon doped after deposition with phosphorus. However, in-situ doping of phosphorus and boron requires fine-tuning of the dopant injection system and obtaining uniform in-situ doping is problematic. The problem of uniformity becomes significantly more acute when attempting to carry out in-situ doping of arsenic. Arsenic is a very desirable dopant because of its low diffusivity. This uniformity problem has been addressed to some extent by employing furnaces having loadlocks and a relatively complex array of injectors.
Furthermore, the deposition rate decreases considerably during phosphorus in-situ doping or arsenic in-situ doping.
Accordingly, providing an improved technique for achieving reduced contact resistance would be desirable.
SUMMARY OF INVENTION
The present invention makes it possible to provide for reduced contact resistance. The present invention makes it possible to achieve reduced contact resistance employing conventional furnaces for doping without requiring loadlocks or a complex array of injectors. In addition, the present invention makes it possible to achieve uniform doping with any conventional dopant including phosphorus, boron and even arsenic.
In one aspect, the invention encompasses a semiconductor structure exhibiting reduced contact resistance. The structure comprises an epitaxial monocrystalline silicon substrate, an insulator layer over the epitaxial monocrystalline silicon substrate, a via etched through the insulator layer to the epitaxial monocrystalline silicon substrate in a limited area, and a contact material in the via in contact with the epitaxial monocrystalline silicon substrate, the 500 Å of the contact material closest to the epitaxial monocrystalline silicon substrate being an amorphous silicon-derived material having an average dopant concentration of at least about 10
20
dopant atoms per cm
3
. The 500 Å portion of the contact may contain layers of undoped amorphous silicon derived material alternating with doping layers, such that the doping layers are separated by undoped amorphous silicon-derived layers.
In another aspect, the invention encompasses a method for fabricating a semiconductor structure having reduced contact resistance. The method of the invention comprises depositing by chemical vapor deposition onto an exposed epitaxial monocrystalline silicon substrate contact surface, layers of undoped amorphous silicon interspersed with dopant layers which are formed by flowing a dopant chemical species over one or more of the deposited amorphous silicon layers. The methods of the invention preferably provide a doped layer of amorphous silicon-derived material having an average bulk dopant concentration of at least about 10
20
atoms/cm
3
within the first 500 Å thickness.
These and other aspects of the invention are described in further detail below.
REFERENCES:
patent: 5773891 (1998-06-01), Delgado et al.
Thakur et al, Novel Method for Deposition of in situ Arsenic-Doped Polycrystalline Silicon Using Conventional Low Pressure Chemical Vapor Deposition Systems,Appl. Phys. Lett.65 (22), Nov. 28, 1994: 2809-2811.
Drynan et al, Fabrication of Polysilicon Plugs for Deep-Submicron Contact-Holes,VMIC Conference, Jun. 12-13, 1990: 441-443.
Economikos Laertis
Faltermeier Johnathan
Park Byeongju
Capella Steven
International Business Machines - Corporation
Pollock Vande Sande & Amernick
Potter Roy
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