Data processing: artificial intelligence – Neural network – Structure
Reexamination Certificate
1999-06-09
2001-08-28
Chaki, Kakali (Department: 2122)
Data processing: artificial intelligence
Neural network
Structure
C706S026000, C706S045000
Reexamination Certificate
active
06282530
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a neural node, and more particularly to a digital neural node through which digital data can be directly, rapidly transmitted among externally coupled information processing units without any additional signal conversion.
2. Description of the Related Art
For manufacturing consumer products with human senses-like functions, a widely used parallel-processing CPU can no longer meet requirements. Instead, a neural network having a plurality of artificial neurons is used to perform the human senses-like functions. A neural network, an information processing unit, is inspired by the way in which a human brain performs a particular task or function of interest. Furthermore, in a neural network, there exits a plurality of neural nodes which are electrically coupled among a plurality of neurons. The neural nodes mainly serves as communication bridges among the plurality of neurons coupled thereto.
FIG. 1
is a block circuit diagram illustrating an analog neutral node according to the prior art. Referring to
FIG. 1
, an analog neural node
10
consists essentially of a resistor R. One end of the resistor R is electrically coupled to ground while the other thereof is electrically coupled to neurons
12
,
14
and
16
. Each of the neurons
12
,
14
and
16
includes a CPU, an analog/digital converter (ADC), a digital/analog converter (DAC).
As to the operation of the above-stated analog neural node
10
, when each neuron transmits a digital data signal to the other neutrons, the internal DAC thereof first converts the transmission required digital data signal into an analog data signal by adding a different level of DC signal and then, outputs the analog data signal to the analog neural node
10
. At this time, other neurons can read the analog data signal from the analog neural node
10
and convert it into the original digital data signal according to the different DC level signal by using the ADCs thereof. As can be known from the above, the analog neural node
10
is only used to serve as a data communication bridge among the neurons
12
,
14
and
16
.
Although digital data can be transmitted among the neurons
12
,
14
and
16
through the analog neural node
10
, the analog neural node
10
has the following disadvantages:
(1) The data transmission rate through the analog neural node is limited by conversions between digital and analog signals and is also limited by bit-by-bit data transmissions;
(2) The number of the externally coupled neurons cannot be unlimitedly increased because each digital data signal to be transmitted must be converted into a corresponding analog data signal by adding a different level of DC signal (i.e., the levels of DC signals are limited);
(3) Additional ADCs and DACs for each neuron must be used, causing higher power consumption; and
(4) Additional ADCs and DACs for each neuron must be used, resulting in higher costs.
SUMMARY OF THE INVENTION
To resolve the above-stated problems, the invention provides a digital neural node. The inventive digital neural node, electrically coupled to n information process units (n is an integer larger than 1), includes n data access devices, each data access device having an input port, a first output port, a second output port, a third output port, . . . and an (n−1)th output port. Each data access device is electrically coupled to a uniquely corresponding information processing unit through the input port and is electrically coupled to the other information processing units through the first output port, the second output port, the third output port, . . . and the (n−1)th output port, respectively. In accordance with the digital neural node, each information processing unit can write digital data in a uniquely corresponding data access device, and the other information processing units can simultaneously read the digital data.
The inventive digital neural node not only resolves the problems of the conventional analog neural node, but also has the following advantages:
(1) The number of the input/output ports is expandable;
(2) The data transmission rate among the information processing units is independent of the number of the information processing units externally coupled;
(3) Since digital data are directly transmitted without any signal conversion, a higher data transmission rate can be obtained; and
(4) Regardless of the number of the information processing units electrically coupled to the digital neutral node of the invention, each information processing unit has a unique path (i.e., a uniquely corresponding data access device electrically coupled) through which digital data can be directly, rapidly transmitted to the other information processing units. Therefore, it is one of reasons to cause the data transmission rate increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5504839 (1996-04-01), Mobus
patent: 5515477 (1996-05-01), Sutherland
patent: 5742741 (1998-04-01), Chiueh et al.
patent: 5751913 (1998-05-01), Chiueh et al.
Johansson, H.O.; Larsson, P.; Larsson-Edefors, P.; Svensson, C., A 200-MHz CMOS bit-serial neural network, ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International, 1994, pp.: 312-315.*
Douglas, R.J.; Mahowald, M.A.; Martin, K.A.C., Hybrid analog-digital architectures for neuromorphic systems, Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE, International Conference on, vol.: 3, 1994, pp.: 1848-.*
Hung, D.L.; Jun Wang, A FPGA-based custom computing system for solving the assignment problem, FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on, 1998, pp.: 298-299.
Chaki Kakali
Helios Semiconductor Inc.
Huang Jiawei
J.C. Patents
Starks, Jr. Wilbert L.
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