Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-09-07
2001-06-26
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C216S091000, C216S079000, C438S723000, C438S724000, C438S745000
Reexamination Certificate
active
06251786
ABSTRACT:
BACKGROUNG OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing dishing and erosion of the copper surface during and after copper Chemical Mechanical Planarization (CMP).
(2) Description of the Prior Art
With continued micro-miniaturization of semiconductor devices and device features, the conductivity of the metal interfaces that are used to interconnect these devices takes on increased importance. It is for this reason that increased emphasis is being placed on finding low resistivity materials and on mastering the art of using these materials in the manufacturing of semiconductor devices. The most widely used material for metal interconnects since the start of the semiconductor industry has been aluminum. Aluminum does however, for very small devices, impose limitations in line-width whereby electromigration is one of the major drawbacks to the use of aluminum in the manufacturing of micron and sub-micron devices. Substitute metals, such as copper, gold and silver are therefore actively investigated since, in addition to low resistivity, these metals offer better resistance to electromigration.
Where the replacement metals that are being investigated as yet present serious problems is in their formation of undesirable inter-metallic alloys and/or in the formation of recombination centers in other parts of the semiconductor device while some of these metal are also prone to have high rates of diffusivity making their application more difficult. Copper is the metal that in recent years has experienced an intense level of investigation relating to both its basic application and in methods of eliminating undesirable side effects where copper is being used. Copper offers the advantages of low cost and ease of processing but suffers from the serious side effect that copper oxidation takes place at relatively low temperatures.
During standard processes of interconnect line formation, photoresist is used to define and during the etching of the required interconnect line pattern. After the etch of this line pattern has been completed, the photoresist must be removed which is performed in a highly oxidized environment thereby exposing the copper to the process of oxidation. The photoresist can, for instance, be removed using an oxygen plasma that reduces the photoresist to an ash that can readily be removed.
Two widely used approaches in creating metal interconnects is the use of the damascene and the dual damascene structures. The application of the Damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etch where the Damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale integrated devices. Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices.
In the formation of a damascene structure, a metal plug is first formed in a surface; this surface in most instances is the surface of a semiconductor substrate. A layer of Intra Level Dielectric (ILD) is deposited (using for instance Plasma Enhanced CVD technology with SiO
2
as a dielectric) over the surface into which trenches for metal lines ate formed (using for instance Reactive Ion Etching technology).
The trenches overlay the metal plug and are filled with metal (use for instance either the CVD or a metal flow process). Planarization of this metal to the top surface of the layer of ILD completes the damascene structure. Some early damascene structures have been achieved using Reactive Ion Etching (RIE) for the process of planarization but Chemical Mechanical Planarization (CMP) is used exclusively today.
An extension of the damascene process is the dual damascene process whereby an insulating or dielectric material, such as silicon oxide, is patterned with several thousand openings for the conductive lines and vias, which are filled at the same time with metal. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. One of the dual damascene approaches uses a dielectric layer that is formed by three consecutive depositions whereby the central layer functions as an etch stop layer. This etch stop layer can be SiN, the top and bottom layer of this three layer configuration can be SiO
2
. This triple layer dielectric allows first forming the vias by resist patterning the vias and etching through the three layers of dielectric. The conductive pattern can then be formed in the top layer of dielectric whereby the central layer of SiN forms the stop layer for the etch of the conducting pattern. Another approach, still using the three-layer dielectric formed on the substrate surface, is to first form the pattern for the conducting lines in the top layer of the dielectric whereby the SiN layer again serves as etch stop. The vias can then be formed by aligning the via pattern with the pattern of the conducting lines and patterning and etching the vias through the etch stop layer of SiN and the first layer of dielectric. Yet another approach is to deposit the three layer dielectric in two steps, first depositing the first layer of SiO
2
and the etch stop layer of SiN. At this point the via pattern can be exposed and etched. The top layer of SiO
2
dielectric is then deposited; the conducting lines are now patterned and etched. The SiN layer will stop the etching except where the via openings have already been etched.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
Due to the fact that copper is very difficult to process by RIE, the CMP method may need to be used where copper is used as a wiring material. To polish copper at a high rate without scratching the buried wiring formation, the copper etch rate must be raised by increasing the amount of the component responsible for copper etching contained in the polishing slurry. If the component is used in an increased amount, the etching will occur isotropically. Consequently, buried copper is etched away, causing dishing in the wiring.
It has already been indicated that copper is often preferred due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper however exhibits the disadvantage of high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. This leads to, for instance, the diffusion of copper into polyimide during high temperature processing of the polyimide resulting in severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required. A barrier layer can typically contain a variety of elements such as combinations of one or more of the elements of titanium with titanium nitride with tungsten or tungsten nitride, tungsten, tantalum, niobium, molybdenum. The invention uses a barrier layer that is Tantalum (Ta) based, other types of barrier layers such as barrier layers that contain tungsten or titanium or their compounds can also be applied within the scope of the invention.
For the dual damascene structure that uses copper for the metal interconnects, in combination with Ta and/or a Ta compound as barrier layer, the dishing of large trenches and the erosion of small device features becomes excessive after the process of CMP of the copper surfaces due to the high selectivity of copper to Ta-based material. This high selectivity is caused by the hard and chemically inert nature (and therefo
Gupta Subhash
Ho Paul Kwok Keung
Zhou Mei Sheng
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L.S.
Powell William
Saile George O.
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