Method and apparatus to control cache memory in multiprocessor s

Details Method and apparatus to control cache memory in multiprocessor s Method and apparatus to control cache memory in multiprocessor s

1995-02-21

1998-04-07

Robertson, David L.

395468, 395473, G06F 1314

Patent

active

057375682

ABSTRACT:
In a multiprocessor system having a shared memory containing the state of the data for every entry in each cache memory possessed by each processor. The state of the data is set to a "shared state" when the data is shared with other cache memories, and is set to a "shared stale state" when the data in the "shared state" becomes stale by updating performed in another cache memory. Each processor monitors a transaction generated on a bus, derives a data portion from the bus when it is in the same address as the data in the "shared stale state" of its own cache memory, thereby updating the data in the address and making the state of the data a "shared state".

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