Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-07-27
2001-08-21
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S391000
Reexamination Certificate
active
06278187
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device comprising an interlayer insulating film with openings formed therein, and electrodes formed by filling the inside of the opening with a conductive substance.
2. Background Art
The width of an internal wiring pattern or the size of an interconnect opening are decreased as the density of integration of a semiconductor integrated circuit is increased. It has been attempted that a surface of an interlayer insulating film is leveled or smoothed to form a minute resist pattern by photolithography, and thereafter a metal plug is formed by filling a conductive substance into the inside of a minute interconnect opening.
In order to fill a conductive substance inside the interconnect opening formed in the interlayer insulating film, there has been a widely used method by which a conductive substance is formed over the entire surface of a wafer and is etched anisotropically. This manufacturing method will now be described with reference to
FIGS. 15 through 19
.
First, as shown in
FIG. 15
, on a semiconductor substrate
1
, an isolation oxide film
2
, gate electrodes
3
, source/drain regions
4
for forming transistors, and a first interlayer insulating film
5
are formed in this sequence. Thus, the semiconductor wafer
100
is formed.
First interconnect openings
6
are formed in the first interlayer insulating film
5
until they reach the source/drain regions
4
. The first interlayer insulating film
5
works to electrically insulates the gate electrodes
3
and to form a smooth surface on the wafer. More specifically, in order to accurately form a resist pattern by the photolithography at the time of formation of the first interconnect openings
6
or formation of a first wiring layer (which will be described later) on the first interlayer insulating film
5
, it is significantly important to ensure a sufficient focal depth by smoothing the surface of the wafer through use of the first interlayer insulating film
5
.
Next, as shown in
FIG. 6
, a conductor film (not shown) is formed over the entire internal surface of each of the first interconnect openings
6
. A chemical vapor deposition technique is usually used for filling the inside of each minute-diameter interconnect opening
6
with a conductive substance without a void. In many cases, polycrystalline silicon, amorphous silicon, metal having a high melting point such as W, TiN or TiSi, or their compounds are used as material for a conductor film.
Subsequently, the conductor film is removed from the surface of the first interlayer insulating film
5
by subjecting the entire surface of the wafer to anisotropic etching. As a result, a first conductor plug
8
is formed in only the inside of each first interconnect opening
6
. In consideration of the uniform thickness of the conductor film and the uniformity of the wafer surface after the etch-back, the wafer is usually etched to a depth which is equal to or greater than the thickness of the conductor film, thereby completely removing the conductor film on the surface of the first interlayer insulating film
5
.
As shown in
FIG. 16
, if the wafer is insufficiently etched, etch residues
77
which are part of the conductor film are left on the surface of the wafer
100
. If a first wiring layer (which will be described later) is formed over the surface of the wafer
100
in this state, electrical short circuits among wiring patterns may be caused. To prevent such failures, the wafer is usually etched to a depth which is greater than the thickness of the conductor film. As shown in
FIG. 17
, the wafer
100
is subjected to an etch-back treatment so as to completely eliminate etch residues from the surface of the wafer.
As mentioned previously, under the conventional method by which the conductor plug
8
is formed inside the interconnect opening
6
by anisotropically etching back the conductor film formed on the surface of the interlayer insulating film
5
, the wafer is over-etched so as to prevent etch residues from being left on the surface of the wafer
100
. For this reason, the surface of the first conductor plug
8
after over-etching is usually recessed about hundreds to thousands Angstroms below the surface of the first interlayer insulating film
5
.
Next, as shown in
FIG. 18
, a second interlayer insulating film
9
is thinly formed on the wafer so as to cover the first interlayer insulating film
5
and the first conductor plug
8
, and then a first wiring layer
10
is formed. The second interlayer insulating film
9
protects the surface of the conductor plug
8
when the first wiring layer
10
is formed by etching.
In recent years, with a view toward increasing the density of integration of a semiconductor integrated circuit device, an interval of the first wiring layers
10
is reduced, and the distance between the first wiring layer
10
and the first interconnect opening
6
are simultaneously reduced. If alignment errors arise during photolithography, the first wiring layer
10
may be formed so as to be partly superimposed on the first conductor plug
8
. At that time, the second interlayer insulating film
9
prevents an electrical short circuit between the first wiring layer
10
and the first conductive plug
8
.
If the surface of the first conductor plug
8
is recessed to a depth (D) of hundreds or more of Angstroms, a recess having substantially the same depth is formed on each conductor plug
8
even after formation of the second interlayer insulating film
9
. Then, an etch residue
11
may remain in each recess after the first wiring layer
10
has been formed by etching.
Next, a third interlayer insulating film
12
is formed on the wafer, and the second interconnect openings
13
is formed through the third interlayer insulating film
12
to the surface of each first conductor plug
8
. Then, the second interconnect openings
13
is filled with a second conductor plug
14
. At this time, the etch residue
11
left in the first interconnect opening
6
may cause a failure such as an electrical short circuit between the first wiring layer
10
and the second conductor plug
14
.
FIGS. 20 and 21
are illustrations for explaining the drawbacks in the conventional semiconductor integrated circuit.
FIG. 20
is a plan view showing a first wiring layer
10
which is formed by the photolithography and through anisotropic etching.
FIG. 21
is a cross-sectional view showing the cross-sectional structure of a wafer taken across line XXI—XXI shown in FIG.
20
. These drawings corresponds to the manufacturing process shown in FIG.
18
.
The first wiring layer
10
should be formed like a wiring pattern
10
a
. However, the first wiring layer such as wiring pattern
10
b
or
10
c
may be formed on the recess formed on the conductor plug
8
, so that the etch residue
11
may be formed along the step of each recess. Although the etch residues
11
are insulated from the first conductor plugs
8
by the presence of the second interlayer insulating film
9
, the etch residue
11
is in continuation with the first wiring layer
10
.
Accordingly, as shown in
FIG. 19
, when the second conductor plugs
14
are formed, the first wiring layer
10
causes short circuits with the first conductor plug
8
and the second conductor plug
14
by way of the etch residue
11
, thereby resulting in a failure.
In addition, as shown in
FIGS. 16 through 19
, a modified layer
55
is formed along the surface of the first interlayer insulating film
5
by means of fluorine-containing etching gas commonly used for etching back a conductor film
7
. The modified layer causes the deterioration of electrical insulating characteristics of the interlayer insulating film
5
. If a wiring layer is formed directly on the surface of the interlayer insulating film
5
, a short-circuit failure may arise between the wiring patterns.
Further, when the second inte
Chibahara Hiroyuki
Iwasaki Masanobu
Sakai Yuichi
Takata Yoshifumi
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Potter Roy
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