Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-12-02
2001-04-24
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S379000, C257S528000, C257S533000
Reexamination Certificate
active
06222247
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a resistor positioned on a semiconductor wafer, and more particularly, to a semiconductor resistor for withstanding high voltages.
2. Description of the Prior Art
Resistors used in high voltage circuits, such as radio frequency integrated circuits (RFIC), microwave frequency integrated circuits or high power integrated circuits, are typically formed in a rectangular-shaped spiral and have a large surface area. This enables them to withstand high voltages.
Please refer to
FIG. 1
to FIG.
3
.
FIG. 1
is a top view diagram of a first doped layer
14
and a second doped layer
16
of a prior art semiconductor resistor
10
for withstanding high voltages.
FIG. 2
is a cross-sectional diagram along line
2
—
2
of the semiconductor resistor
10
shown in FIG.
1
.
FIG. 3
is a cross-sectional diagram of the prior art semiconductor resistor
10
. The prior art semiconductor resistor
10
for withstanding high voltages is formed on an n-type silicon substrate
12
of a semiconductor wafer. The semiconductor resistor
10
comprises a first doped layer
14
that functions as a resistor for withstanding high voltages in a predetermined area on the silicon substrate
12
, a second doped layer
16
formed in a predetermined area of the first doped layer
14
; a dielectric layer
18
positioned on the surface of the silicon substrate
12
, the first doped layer
14
and the second doped layer
16
; and a passivation
20
layer positioned on the dielectric layer
18
. The first doped layer
14
is p-type and the second doped layer
16
is n-type. The junction of the first doped layer
14
and silicon substrate
12
forms a pn-junction to prevent electrical leakage.
The resistor
10
is made by implanting ions in a predetermined area on the silicon substrate
12
to form the p-type doped layer
14
, as shown in FIG.
2
. The first doped layer
14
is formed in a strip-like area that is shaped approximately like a square wave within the predetermined area. The second doped layer
16
, that is similar to the first doped layer
14
in shape, is formed by implanting ions in a predetermined area within the first doped layer
14
.
The dielectric layer
18
is then deposited on to the silicon substrate
12
, the first doped layer and the second doped layer. Contact windows (not shown) are formed at the two ends of the resistor by lithography and etching. Contact windows are used to connect the resistor
10
with other devices on the semiconductor wafer. Finally, the passivation layer
20
is deposited on the surface of the resistor
10
to complete the resistor
10
.
With the deposition of the passivation layer
20
, some charged ions are mixed with the depositing particles, and a plurality of charges at fixed positions are generated. An electric field is generated by this charge in the passivation layer
20
when the resistor
10
is connected. This reduces the breakdown voltage of the pn-junction of the silicon substrate
12
and the doped layer
14
and generates electrical leakage. Since the doped layer
14
is formed on the silicon substrate
12
in a strip-like area that is shaped approximately like a square wave, it forms right-angled corners. When the resistor is used at high voltages, a strong electric field is generated at the right-angled corners of the doped layer. This reduces the voltage value of the resistor
10
.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a resistor for withstanding high voltages; the resistor can prevent electrical leakage and the reduction of the breakdown voltage caused by electric fields induced by fixed charges in the passivation layer.
In a preferred embodiment, the present invention provides a semiconductor resistor formed in a predetermined area on the surface of a semiconductor wafer, the semiconductor wafer comprising a silicon substrate doped with first-type dopants, the first-type being either n-type or p-type, the resistor comprising:
a first doped layer in a strip-like area approximately spiral in shape within the predetermined area, the first doped layer formed by ion implantation of second-type dopants and serving as a resistor, the second-type being either n-type or p-type and different from the first-type;
a plurality of second doped layers formed by ion implantation along the strip-like area of the first doped layer, the dopant density of the second doped layers being larger than that of the first doped layer;
a trench formed in the substrate and adjacent to the strip-like area of the first doped layer, the depth of the trench being less than that of the first doped layer;
a first dielectric layer formed on the surface of the first doped layer, the second doped layers and the trench;
a second dielectric layer formed on the surface of the first dielectric layer within the trench and filling the trench; and
a passivation layer formed on the first dielectric layer and the second dielectric layer.
It is an advantage of the present invention that the resistor for withstanding high voltages can prevent electrical leakage and avoids the reduction of the breakdown voltage caused by electric fields induced by fixed charges in the passivation layer.
REFERENCES:
patent: 4511789 (1985-04-01), Goessler et al.
patent: 4721985 (1988-01-01), Pavlidis et al.
patent: 4792840 (1988-12-01), Nadd
patent: 5053743 (1991-10-01), Mille et al.
Hsu Winston
Meier Stephen D.
United Microelectronics Corp.
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