Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1998-05-07
2001-04-24
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S686000, C257S687000, C257S722000, C257S723000, C257S725000, C257S701000, C257S676000, C257S678000, C257S666000, C257S784000
Reexamination Certificate
active
06222260
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuit devices and more specifically to integrated circuit devices with decoupling capacitors.
BACKGROUND ART
As ultra large-scale integrated circuits have continued to evolve, they have become more complex with the need to switch more and more output driver circuits at higher and higher speeds. In addition, an increase in the use of parallel processing has necessitated designing circuits with a high number of driver circuits to switch simultaneously at fast transition speeds and high currents. Since the effective inductance of semiconductor chips for these active switching circuits is directly related to the amount of power distribution noise, the driver circuit power connections are particularly sensitive to the noise created by the effective inductance inherent in simultaneous switching activity. Numerous techniques have been developed using decoupling capacitors to reduce power supply transients, ground bounce, and high frequency inductive delay.
The earliest techniques involved positioning the decoupling capacitors as discrete components on the printed circuit board adjacent to the integrated circuit device. However, the length of the connections of the decoupling capacitors to the integrated circuit devices added unwanted inductances and introduced further noise.
Since it is desirable to have the decoupling capacitors as close to the integrated circuit as possible to maximize the benefits of the decoupling capacitor, subsequent designs located the decoupling capacitors as small, discrete devices above or below the associated integrated circuit device. While this approach provided some improvement, the difficulty of making the manufacturing interconnections to the integrated circuit device or to the circuit board and the still relatively long connections continued to be less than optimal.
Subsequently, many different approaches were developed to photolithographically place the decoupling capacitors “on-chip” on the semiconductor chips themselves.
Where the decoupling capacitors were placed on the surface of the silicon chip as part of the integrated circuit, maximum reduction of negative effects was achieved, but at an exorbitant cost in highly valuable silicon real estate.
Where the decoupling capacitors were integrated over the circuitry of the semiconductor chips as part of the semiconductor manufacturing process, additional processing steps were required which introduced additional complexity, which reduced yield and made the resulting integrated circuits more expensive.
A simple, elegant solution has long been sought for providing inexpensive integrated circuit devices with decoupling capacitors that reduce power supply transients, ground bounce, and high frequency inductive delay. As indicated by the many different approaches to the inherent problems, a solution has long eluded those skilled in this art.
DISCLOSURE OF THE INVENTION
The present invention provides an integrated circuit device having a planar decoupling capacitor integral with a planar semiconductor chip and a planar bonding element. The three are coplanar and located in a fixed relationship which places the planar decoupling capacitor as close to the planar semiconductor chip as possible without having the performance problems of being outside the integrated circuit device or having the processing problems of being on-chip.
An advantage of the present invention is to provide an integrated circuit device having an integral decoupling capacitor which provides semiconductor chip performance improvements while being easily manufactured with current technology.
Another advantage of the present invention is to provide an integrated circuit device in which the decoupling capacitor is close to the semiconductor chip to reduce ground bounce in the semiconductor chip.
Another advantage of the present invention is to provide an integrated circuit device in which the decoupling capacitor is close to the semiconductor chip to reduce crosstalk in the semiconductor chip.
Another advantage of the present invention is to provide an integrated circuit device in which the decoupling capacitor is close to and positioned to shield the semiconductor chip to reduce electro-magnetic interference from the semiconductor chip.
Another advantage of the present invention is to provide an integrated circuit device in which the decoupling capacitor is close to the semiconductor chip and can provide a large capacitance to the semiconductor chip.
Another advantage of the present invention is to provide an integrated circuit device in which the decoupling capacitor is close to the semiconductor chip and can provide a number of different capacitances to the semiconductor chip.
Another advantage of the present invention is to provide an integrated circuit device with an integral decoupling capacitor which is easy to assemble and is easily compatible with current device assembly processes.
Another advantage of the present invention is to provide an integrated circuit device with an integral decoupling capacitor which is more compact than conventional combinations of the semiconductor chip with a separate decoupling capacitor.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
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Killorn Ray
Liang Dexin
Ishimaru Mikio
Thai Luan
Thomas Tom
VLSI Technology Inc.
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