Method and circuit for checking lead defects in a two-wire...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S537000

Reexamination Certificate

active

06249127

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
This application claims the priority of German Application No. 197 26 538.3, filed Jun. 23, 1997, the disclosure of which is expressly incorporated by reference herein.
The present invention relates to a method and a circuit for checking lead defects in a two-wire bus system in which a check for lead defects in a two-wire bus system is performed by comparing the voltage levels on the two wires with certain threshold values. The comparison with the threshold values takes place in a dominant and a recessive state.
A method is already known (see German Patent document DE 42 12 742 A1) in which preferably two end stages of at least one bus subscriber are controlled. The voltages that prevail on the two wires of the bus system are checked by two control leads, with these two control leads being supplied though an A/D converter to the input of a microprocessor. In addition, a table of voltage values is provided which are established when the two end stages are controlled on the two wires of the two-wire bus system as a function of various defect cases. Defect cases of this kind can consist for example of a short circuit to ground, a short circuit to the potential of the supply voltage, a short circuit between the two wires, or a wire break. When the voltage values on the two wires are detected in the microprocessor, these voltage values are compared with the values provided in the table in order to unambiguously detect a possible defect and to locate it. Eight voltage values are provided for each of the two wires, depending on whether the system is operating free of defects or whether a defect is present, and if a defect is present, what type of defect it is. Further evaluation therefore becomes comparatively expensive because of the necessity for a comparison of each of the measured voltages with eight voltage values. Even if it is conceivable (something not described in detail in the cited reference, however) that this can be done by means of software in the microprocessor, this method is comparatively costly in design.
It is also known from German Patent document DE 195 09 133 A1 to link the two signal leads of the two-wire bus system to the inputs of comparators. A comparator is provided whose two inputs each receive one of the two signal leads. By means of this comparator, the voltage difference between the two signal leads is determined. In addition, two comparators are provided, to each of whose inputs one of the two signal leads is supplied and with the other input, in each case, receiving a reference voltage that corresponds approximately to the value V
cc
2. From various combinations of the levels of the outputs of the comparators in the dominant as well as recessive states, certain defect situations such as short circuits to ground or to V
cc
can be detected. In addition, a decision can be made as to whether it is possible and/or advisable in certain situations to continue single-wire transmission using the intact lead.
The goal of the present invention is to expand the possibilities of defect detection.
According to the invention this is achieved by a method in which the voltages on the two wires are each compared with a voltage level that is above the maximum voltage value on the wires in the dominant and recessive states during normal operation.
As a result, it is possible to detect a short circuit of one or both wires to the system and/or battery voltage U
Batt
. Otherwise, it is possible to detect only a short circuit to ground or to V
cc
.
In contrast to the procedure in German Patent document DE 42 12 742 A1, it is advantageous that the checking of the voltage ratios in the two states defined requires fewer threshold values to perform the check. Otherwise, the check can be performed during normal transmission without a special test situation having to be created as described in DE 42 12 742 A1.
With the method according to the present invention, dimensioning is provided that allows the voltage levels on the two wires to be compared in the simplest case to detect a defect. Accordingly, the voltages on the two wires are each compared with a voltage level that is between the two voltage values on the wires in the dominant and recessive states during normal operation.
In a further advantageous method according to the invention, in combination with the method steps described or also according to the invention without these method steps, a comparison is made between the voltage differential between the voltages on the two wires in the dominant and recessive states, and predetermined threshold values. As a result, a possible defect can be further pinpointed.
Advantageously, a possible defect can be further pinpointed using the method according to a preferred embodiment of the invention, with the voltage differential between the voltages on the two wires being monitored for a first voltage level being exceeded, and for the voltage level lying within a window that is specified by a second and a third voltage level, with the first voltage level being above the second and third voltage levels.
A circuit according to the invention for working one of the above methods, has an input of a first comparator being connected with one wire and has an input of a second comparator being connected with the other wire. The other inputs of the first and second comparators each are subjected to a voltage that is between the two voltage values on the wires in the dominant and recessive states during normal operation. One input of a third comparator is connected with one wire, and an input of a fourth comparator is connected with the other wire. The other inputs of the third and fourth comparators each are subjected to a voltage that is above the maximum voltage value on the wires in the dominant and recessive states during normal operation. The outputs of the first and second comparators are supplied to a subtractor, with voltage adaptation of the level of the output signal taking place. The output signal of the subtractor is supplied to the input of a fifth comparator. The output signal from the subtractor also is supplied through a diode to the input of a window comparator. The outputs of the third and fourth comparators are connected with the input of the window comparator.
With this circuit, therefore, a distinction can be made between various defects, with the number of voltage comparators being advantageously limited relative to the previously known prior art.
In an improvement on the circuit according to the present invention, the outputs of the first, second, and fifth comparators as well as of the window comparator are evaluated in order to determine the state of the wires.
By evaluating the outputs of the comparators, it is advantageously no longer necessary to determine the voltage by means of an A/D converter, which is advantageous as far as cost is concerned. Furthermore, at the voltage levels that can be set as threshold values according to the present invention, it turns out that these voltage levels are located much further apart than shown in the table in German Patent document DE 42 12 742 A1 to distinguish the individual defects. A difference in the voltage level on the order of several tenths of a volt for example can be caused by a ground mismatch that results in a poor contact with ground.
Hence, the solution according to the invention considerably increases accuracy in pinpointing a defect that occurs.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.


REFERENCES:
patent: 3727128 (1973-04-01), McFerrin
patent: 3833853 (1974-09-01), Milford
patent: 4144487 (1979-03-01), Pharney
patent: 4151459 (1979-04-01), Fayolle et al.
patent: 4165482 (1979-08-01), Gale
patent: 4491782 (1985-01-01), Bellis et al.
patent: 4728898 (1988-03-01), Staley, Jr.
patent: 5184081 (1993-02-01), Oswald et al.
patent: 5781585 (1998-07-01), Doener et al.
patent: 42 12 742 A1 (1993-10-01), None
pat

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