Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-03-01
2001-08-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S118000, C257S685000, C257S686000
Reexamination Certificate
active
06271056
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor packaging. More particularly, this invention relates to an improved semiconductor package having a stacked configuration and containing multiple semiconductor dice, and to a method for fabricating the package.
BACKGROUND OF THE INVENTION
Semiconductor dice or chips are typically contained in semiconductor packages. This is sometimes referred to as the first level of packaging. The package is required to support, protect, and dissipate heat from a die, and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and full functionality testing of the die.
In general, conventional plastic and ceramic packages incorporate several common elements. These common elements include a sealed package enclosure, a die attachment area, bond wires for establishing electrical communication with bond pads on the die, and a lead system for the package. One shortcoming of a conventional semiconductor package is that a peripheral outline (i.e., footprint) of the package is typically much larger than that of the die contained within the package (e.g., 10× or more). In addition, the manufacturing processes for conventional packages are relatively complicated, and require large capital expenditures.
Another type of package is referred to as a ball grid array (BGA) package. With this type of package, a substrate formed of a glass filled resin, or similar material, includes patterns of conductors in electrical communication with arrays of external contacts. One or more dice can be wire bonded to the conductors, and protected by a plastic material, such as a glob top encapsulant. A ball grid array package has a peripheral outline that is on the order of two to eight times that of the die. While the size is an improvement over conventional packages, this type of package also requires relatively complicated manufacturing processes, and has not received widespread acceptance in the industry.
Yet another type of package is referred to as a chip scale package. Typically, a chip scale package includes a substrate bonded to a face of a single die. The substrate includes external contacts for the package, such as solder balls in a ball grid array (BGA), or in a fine ball grid array (FBGA). The substrate for a chip scale package can comprise a flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, or a glass filled resin. A chip scale package has a peripheral outline that is about the same as that of the die contained within the package (e.g., 1.2×). However, volume manufacture of chip scale packages has proven to be difficult. In particular forming reliable electrical connections between the die and substrate requires specialized equipment and techniques.
The present invention is directed to a semiconductor package that is simpler in construction, and cheaper to volume manufacture than any of the above conventional packages. In addition, the package has a relatively small peripheral outline, but is designed for fabrication in a stacked configuration, in which multiple dice can be contained in the same package.
SUMMARY OF THE INVENTION
In accordance with the present invention, a stacked semiconductor package, and a method for fabricating the package are provided. The package comprises a plurality of separate substrates, each having a semiconductor die mounted thereon, in electrical communication with external contacts and contact pads on opposing sides of the substrate. The substrates are configured for stacking to one another with the external contacts on a first substrate, bonded to the contact pads on an adjacent second substrate. In addition, the substrates are configured to provide a small outline package but with multiple semiconductor dice packaged in a high density configuration.
In an illustrative embodiment a first side of a substrate includes a wire bonding cavity having conductors in electrical communication with a pattern of contact pads. A second side of the substrate includes a die mounting cavity, and a matching pattern of external contacts. An interconnect opening is formed through the substrate to provide access for wire bonding to bond pads on the die, and to the conductors on the first side of the substrate. In addition, an encapsulant can be formed within the wire bonding cavity to encapsulate and protect the wire bonds and associated wires. Preferably the encapsulant and the wire bonding cavity are configured to provide a planar surface to facilitate stacking of the substrate. In a similar manner, the die and the die mounting cavity can be configured to provide a planar surface for stacking of the substrate.
The substrate also includes interlevel conductors for electrically interconnecting the contact pads on the first side of the substrate to the external contacts on the second side of the substrate. The interlevel conductors comprise holes through the substrate and containing a metal, or a conductive elastomeric material.
The external contacts are configured for bonding to the contact pads of the adjacent stacked substrate. For example, the external contacts can be formed of a bondable material such as a solder, and the contact pads can be formed of a solder wettable material such as copper. Alternately, the external contacts can comprise a conductive elastomer deposited as a viscous paste, and then cured to form an electrically conductive bond with the contact pads. A conductive elastomer can also be placed between the external contacts and contact pads to form a conductive bond therebetween.
The method of fabrication can be performed using panels containing multiple substrates. Exemplary materials for fabricating the panels include glass filled resins, plastics, ceramic and silicon. Following fabrication of the panels, semiconductor dice can be adhesively bonded to the die mounting cavities on the first sides of the panels, and then wire bonded to the conductors on the second sides of the panels. Following encapsulation of the wire bonds, two or more panels can be stacked to one another, with the external contacts and contact pads on adjacent stacked panels in physical contact. Using a bonding process, such as a solder reflow, or a conductive elastomer curing process, the external contacts and contact pads on the adjacent stacked panels can then be bonded to one another. Following bonding, the stacked panels can be separated into separate packages using a cutting, shearing or breaking process.
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Brooks Mike
Farnworth Warren M.
Wood Alan G.
Gratton Stephen A.
Luk Olivia
Micro)n Technology, Inc.
Niebling John F.
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