Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-01-15
2001-04-24
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S112000, C438S118000, C438S127000, C257S783000, C257S782000, C257S795000, C257S781000, C257S779000
Reexamination Certificate
active
06221691
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor packaging and more particularly to an improved system and method for attaching semiconductor dice to substrates, such as printed circuit boards.
BACKGROUND OF THE INVENTION
One type of semiconductor die, referred to as a “bumped” die, includes patterns of contact bumps formed on a face of the die. The contact bumps can be formed on wettable metal contacts on the die in electrical communication with the integrated circuits contained on the die. The contact bumps allow the die to be “flip chip” mounted to a substrate having corresponding solder wettable contacts. This mounting process was originally developed by IBM and is also known as the C4 joining process (Controlled Collapse Chip Connection).
Lead tin alloys (e.g., 95/5 lead tin alloy) and a ball limiting metallurgy (BLM) process can be used to form the bumps. Typically, the bumps are dome shaped, and have an average diameter of from 5 mils to 30 mils. Micro ball grid arrays (BGA) are formed in the smaller range, while standard ball grid arrays are formed in the larger size range. The sides of the bumps typically bow or curve outwardly from flat top surfaces. The flat top surfaces of the bumps form the actual regions of contact with the mating contacts on the substrate.
FIGS. 1A-1C
illustrate a prior art flip chip mounting process. In
FIG. 1A
a bumped semiconductor die
10
includes a pattern of contact bumps
12
arranged in a desired pattern
14
. As shown in
FIG. 1B
, the die
10
also includes a passivation layer
18
and contacts
16
for the bumps
12
. The contacts
16
are in electrical communication with the semiconductor devices and integrated circuits formed on the die
10
.
Each bump
12
can be formed on a corresponding contact
16
. In addition, each bump
12
can include a stack of underlying layers
20
a-c.
By way of example, layer
20
a
can be an adherence layer (e.g., Cr), layer
20
b
can be a solderable layer (e.g., Cu) and layer
20
c
can be a flash layer (e.g., Au). The bumps
12
can be formed by processes that are known in the art such as ball limiting metallurgy (BLM). Typically, the bumps
12
comprise an alloy such as lead/tin or nickel/palladium.
In
FIG. 1C
the die
10
has been flip chip mounted to a substrate
22
. The substrate
22
includes solder wettable contacts
24
embedded in a glass layer
26
. During the flip chip mounting process the contact bumps
12
(
FIG. 1B
) on the die
10
are aligned and placed in physical contact with the contacts
24
on the substrate
22
. This can be accomplished with an optical alignment device such as an aligner bonder tool. A flux can be placed on the substrate as a temporary adhesive to hold the die
10
in place on the substrate
22
.
The temporary assembly is then subjected to a reflow thermal cycle using a heat source directed at the die
10
or an oven which heats the entire assembly. This melts the contact bumps
12
(
FIG. 1B
) and forms reflowed contact bumps
12
RF. The reflowed contact bumps
12
RF bond the contacts
24
on the substrate
22
to the contacts
16
on the die
10
. In addition, the reflowed contact bumps
12
RF provide separate electrical and heat conductive paths for the die
10
.
In some applications an underfill layer
28
can be formed between the die
10
and the substrate
22
. The underfill layer
28
seals the gap between the die
10
and substrate
22
. In addition, the underfill layer
28
can include a heat conductive material, such as silver balls, to improve heat transfer from the die
10
.
With flip chip mounting the physical attachment of the die
10
to the substrate
22
is formed by the reflowed contact bumps
12
RF. In general, the reflowed contact bumps
12
RF are relatively small in total area so that the attachment force is relatively low. In addition, the reflowed contact bumps
12
RF can crack during subsequent usage of the substrate
22
. This can loosen the die
10
and increase the electrical resistivity of the electrical paths between the die
10
and substrate
22
.
Also during the flip chip mounting process, the die
10
must be held in place while the reflowed contact bumps
12
RF harden from the molten state. Shifting of the die
10
during hardening of the reflowed contact bumps
12
RF, can weaken the attachment forces between the die
10
and substrate
22
. Still further, the die
10
must be pressed against the substrate
22
with a required pressure during the flip chip mounting pressure. This pressure also affects the subsequent attachment force. If the pressure is low or uneven the attachment force can also be low and uneven.
In view of the above limitations of conventional flip chip mounting processes, the present invention is directed to an improved system and method for attaching semiconductor dice to substrates.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved method and system for attaching semiconductor dice to substrates are provided. The method includes the steps of:
heating a bumped die to soften contact bumps thereon;
applying an instant curing adhesive to a die mounting area of the substrate;
aligning the contact bumps with contacts on the substrate;
pressing the die against the die mounting area with a desired pressure; and then curing the adhesive with the heated die to form a cured adhesive layer.
Following curing of the adhesive layer, the reflowed contact bumps harden and bond to the contacts on the substrate. Shrinkage of the adhesive layer during curing places tension forces on the die, and compresses the reflowed contact bumps against the contacts. The tension forces facilitate bonding of the contact bumps to the contacts, and lower the electrical resistivity of the resultant connections. In addition, the adhesive layer permanently attaches the die to the substrate, and eliminates the need for an underfill layer between the die and substrate.
Preferably the adhesive comprises an epoxy, such as a bismaleimide resin, which is curable in seconds at a temperature of from 100-300° C. One suitable material comprises a conductive epoxy in which conductive silver particles are replaced with non-conductive Teflon particles. In addition, the contacts on the substrate can be formed as bumps of a conductive material such as a conductive polymer.
The system comprises a conventional lead-on-chip die attacher modified to align and place the die and substrate in contact. The substrate can include indexing holes to facilitate the alignment process. In addition, the system can include a heating mechanism for heating the die, and a dispensing mechanism for dispensing the adhesive on the die mounting area of the substrate. The system can also include a die pressing mechanism configured to press the die against the adhesive with a desired amount of pressure.
The method and system of the invention can be used to provide an improved electronic assembly. The assembly comprises:
a substrate with patterns of contacts thereon;
a plurality of bumped semiconductor dice having contact bumps bonded to the contacts on the substrate; and cured adhesive layers attaching the dice to the substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A
is a plan view of a prior art bumped semiconductor die including contact bumps arranged in a ball grid array (BGA);
FIG. 1B
is an enlarged cross sectional view of a prior art contact bump taken along section line
1
B—
1
B of
FIG. 1A
;
FIG. 1C
is an enlarged cross sectional view of the bumped die attached to a substrate with a prior art flip chip mounting method;
FIG. 2
is a block diagram illustrating broad steps in the method of the invention;
FIG. 3A
is a schematic plan view of a substrate having an instant cure epoxy deposited onto a die mounting area thereof;
FIG. 3B
is a side elevation view of
FIG. 3A
;
FIG. 4A
is a schematic side view of the substrate and die during an alignment step;
FIG. 4B
is a schematic cross sectional view of the completed assembly; and
FIG. 5
is a schematic diagram of a system constructed in accordance with the invention
Gratton Stephen A.
Keshavan Belur
Micro)n Technology, Inc.
Smith Matthew
LandOfFree
Method and system for attaching semiconductor dice to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for attaching semiconductor dice to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for attaching semiconductor dice to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2493975