Maximum length shift register sequence generator

Details Maximum length shift register sequence generator Maximum length shift register sequence generator

1987-07-07

1989-09-05

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 102

Patent

active

048645257

ABSTRACT:
A maximum length shift register sequence generator comprises: (1) an input terminal for feedback (FB 0); (2) an input terminal to the steering gate of the first stage (FB 1); (3) an output terminal from the exclusive OR gate of the last stage (CAS); (4) a three state output terminal from a multiplexer circuit (FB 2); and (5) a control input terminal of a three state output multiplexer circuit (FBCNT); a plurality of which can be connected in cascade. It includes a flipflop circuit, whose data input is a feedback control signal (FBCNT) controlling within which maximum length shift register sequence generator the output of the multiplexer circuit should be fedback, when they are connected in cascade, and whose clock input is the strobe pulse (STB), the output of this flipflop circuit being the enable input of the three state output multiplexer circuit. It includes further a logical product gate (AND 0), whose inputs are two signals, one being a latch enable pulse ( LE ) for latching, (i) the initial state of the flipflop, (ii) the feedback state, (iii) the last stage selection state for the flipflops, the other being a chip select (CS), and a demultiplexer circuit distributing the output of this logical product gate (AND 0) to the latch circuits for latching the data (i).about.(iii) described above, depending on the two select signals (SEL 0.about.1).

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patent: 4531022 (1985-07-01), Pioli
patent: 4785410 (1988-11-01), Hamatsu et al.

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