Semiconductor circuit components and capacitors

Details Semiconductor circuit components and capacitors Semiconductor circuit components and capacitors

1999-01-13

2001-08-28

Dinkins, Anthony (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S313000, C361S321500, C251S296000

Reexamination Certificate

active

06282080

ABSTRACT:

TECHNICAL FIELD
The invention pertains to semiconductor circuit components and capacitors, and to methods of forming capacitors and semiconductor circuit components.
BACKGROUND OF THE INVENTION
Tantalum pentoxide (Ta
2
O
5
) is a desired capacitor dielectric material due to its high dielectric constant of about 25. In contrast, other commonly utilized dielectric materials have much lower dielectric constants. For instance, silicon nitride has a dielectric constant of about 8 and silicon dioxide has a dielectric constant of about 4. Due to the high dielectric constant of Ta
2
O
5
, a thinner layer of Ta
2
O
5
can be utilized in capacitor constructions to achieve the same capacitance as thicker layers of other materials.
Semiconductive capacitors comprise a first conductive plate and a second conductive plate, with a dielectric layer formed between the plates. Commonly, the conductive plates comprise doped polysilicon, with one or both of the plates comprising a rugged form of polysilicon, such as, for example, hemispherical grain polysilicon.
It is highly desired to utilize Ta
2
O
5
as the dielectric layer due to the dielectric properties discussed above. Unfortunately, the chemical vapor deposition (CVD) processes by which Ta
2
O
5
is formed adversely complicate its incorporation into semiconductive capacitors. For instance, Ta
2
O
5
is not typically deposited onto a first polysilicon plate, nor is a second polysilicon plate typically directly deposited onto Ta
2
O
5
. The CVD processes by which Ta
2
O
5
is formed adversely affect underlying and overlying polysilicon layers unless such polysilicon layers are first protected with barrier layers. Specifically, Ta
2
O
5
is typically formed by a CVD process in which Ta(OC
2
H
5
)
5
and oxygen are combined. Unless a polysilicon plate is protected by a barrier layer before such CVD deposition over the polysilicon, the oxygen of the CVD process will react with the polysilicon to disadvantageously form a layer of silicon dioxide over the polysilicon. Present methods for protecting the polysilicon include provision of a silicon nitride layer over the polysilicon prior to formation of Ta
2
O
5
. The silicon nitride layer is typically 10 to 20 angstroms thick. Also, unless a Ta
2
O
5
layer is first covered with a barrier layer before formation of polysilicon over the Ta
2
O
5
layer, the polysilicon will react with oxygen in the Ta
2 O
5
layer to disadvantageously form silicon dioxide.
An example prior art process for forming a capacitor
10
having a Ta
2
O
5
dielectric layer is illustrated in
FIG. 1. A
polysilicon first capacitor plate
12
is formed over a substrate
14
. A silicon nitride layer
16
is formed over polysilicon layer
12
. A Ta
2
O
5
dielectric layer
18
is formed over silicon nitride layer
16
by the above-described CVD process. After the CVD of Ta
2
O
5
layer
18
, the layer is typically subjected to an anneal in the presence of an oxygen ambient. The anneal drives any carbon present in layer
18
out of the layer and advantageously injects additional oxygen into layer
18
such that the layer uniformly approaches a stoichiometry of five oxygen atoms for every two tantalum atoms. The oxygen anneal is commonly conducted at a temperature of from about 400° C. to about 1000° C. utilizing an ambient comprising an oxygen containing gas. The oxygen containing gas commonly comprises one or more of O
3
, N
2
O and O
2
. The oxygen containing gas is typically flowed through a reactor at a rate of from about 0.5 slm to about 10 slm.
Ta
2
O
5
layer
18
is typically from about 40 angstroms to about 150 angstroms thick and can be either amorphous or crystalline. It is noted that Ta
2
O
5
is generally amorphous if formed below 600° C. and will be crystalline if formed, or later processed, at or above 600° C. Typically, a Ta
2
O
5
layer is deposited as an amorphous layer and the above-described oxygen anneal is conducted at a temperature of 600° C. or greater to convert the amorphous Ta
2
O
5
layer to a crystalline layer.
A second nitride layer
20
is deposited over Ta
2
O
5
layer
18
. Second nitride layer
20
typically comprises TiN or WN. A second capacitor plate
22
is formed over nitride layer
20
. Second capacitor plate
22
, like first capacitor plate
12
, typically comprises doped polysilicon or doped rugged polysilicon. It is noted that the top electrode of the Ta
2
O
5
capacitor can comprise only TiN or WN layer
20
, or can comprise the layer
20
and layer
22
stack.
The formation of layer
20
is typically done by a chemical vapor deposition process, as opposed to a sputtering type process, to achieve acceptable conformity in high aspect ratio capacitor devices. Such CVD processes use either metal organic precursors or organometallic precursors. Either precursor contains carbon and results in the deposition of a barrier layer
20
which typically includes large amounts of carbon, commonly from about 10 to about 15 volume percent, and sometimes as much as 30 volume percent. Although such carbon typically does not adversely impact the function or conductivity of the nitride layer
20
, subsequent wafer processing can cause carbon from layer
20
to diffuse into Ta
2
O
5
layer
18
. Carbon diffusing into Ta
2
O
5
layer
18
can disadvantageously cause layer
18
to leak current, and in extreme cases can convert an intended capacitor device
10
into a device that behaves more like a resistor than a capacitor.
An additional disadvantage that can occur during placement of a nitride barrier layer
20
over Ta
2
O
5
layer
18
is that there is typically some formation of the undesired compound TiO
2
at an interface between Ta
2
O
5
layer
18
and barrier layer
20
.
It would be desirable to develop alternative methods of utilizing Ta
2
O
5
in integrated circuit construction.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses methods of forming a dielectric layer. A first tantalum-comprising layer is formed and a second tantalum-comprising layer is formed over the first tantalum-comprising layer. The second tantalum-comprising layer comprises nitrogen.
In another aspect, the invention encompasses a method of forming a capacitor. A first capacitor plate is formed and a first layer is formed over the first capacitor plate. The first layer comprises tantalum oxide. A second layer is formed over the first layer. The second layer comprises tantalum and nitrogen. A second capacitor plate is formed over the second layer.
In another aspect, the invention encompasses a method of forming a capacitor. A first capacitor plate is formed. A first layer is formed over the first capacitor plate. The first layer comprises tantalum and oxygen, and is substantially void of carbon. A barrier layer is formed over the first layer. A metal nitride layer is formed over the barrier layer. A second capacitor plate is formed over the metal nitride layer. The metal nitride layer is processed at a sufficient temperature to diffuse carbon from the metal nitride layer. The barrier layer substantially prevents the diffused carbon from permeating into the first layer.
In another aspect, the invention encompasses a semiconductor circuit component comprising a first tantalum-comprising layer and a second tantalum-comprising layer over the first tantalum-comprising layer. The second tantalum-comprising layer comprises nitrogen.
In another aspect, the invention encompasses a capacitor. The capacitor comprises a first capacitor plate and a first layer over the first capacitor plate. The first layer comprises tantalum and oxygen. The capacitor further includes a second layer over the first layer. The second layer comprises tantalum and nitrogen. Additionally, the capacitor includes a second capacitor plate over the second layer.


REFERENCES:
patent: 4333808 (1982-06-01), Bhattacharyxa et al.
patent: 4464701 (1984-08-01), Roberts et al.
patent: 4891682 (1990-01-01), Yusa et al.
patent: 4952904 (1990-08-01), Johnson et al.
patent: 5053917 (1991-10-01), Miyasaka et al.
patent: 5079191 (1992-01-01), Shinriki et al.
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