Frequency multiplier capable of generating a multiple output...

Details Frequency multiplier capable of generating a multiple output... Frequency multiplier capable of generating a multiple output...

2000-03-08

2001-06-12

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S119000, C327S122000

Reexamination Certificate

active

06246271

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.
11-064587
, filed Mar. 11, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a frequency multiplier capable of generating a multiple output without feedback control (by non-feedback control). More specifically, the present invention relates to a frequency multiplier for use in a clock generator of a microcomputer, a DSP (digital signal processor) and the like.
Conventionally an N multiplier using a PLL (phase locked loop) circuit has been known well as a frequency multiplier.
FIG. 1
shows an example of an arrangement of a generally-used N multiplier employing a PLL circuit. The N multiplier includes a voltage control oscillator
101
, an N frequency divider
102
, a phase comparator
103
and a low-pass filter
104
. The N multiplier performs feedback control to cancel a phase difference between a reference signal Fin and an output of the N frequency divider
102
. Finally, the voltage control oscillator
101
generates an output signal Fout whose frequency is N times as high as that of the reference signal Fin. In other words, the oscillation frequency of the voltage control oscillator
101
is varied by a control voltage output from the low-pass filter
104
. The N frequency divider
102
supplies the phase comparator
103
with a signal obtained by N-dividing an output of the voltage control oscillator
101
. The phase comparator
103
supplies the low-pass filter
104
with an error signal corresponding to a phase difference between the reference signal Fin and the rising (or falling) edge of a signal output from the N frequency divider
102
. The low-pass filter
104
extracts only the DC components from the error signal output from the phase comparator
103
and generates a control voltage for controlling the oscillation frequency of the voltage control oscillator
101
.
In the above-described conventional N multiplier using a PLL circuit, however, it was necessary to optimize and adjust the low-pass filter
104
such that a control loop could be constantly stabilized in accordance with both a frequency of the reference signal Fin and an oscillation gain of the voltage control oscillator
101
. For this reason, the low-pass filter
104
had to be optimized every time the frequency of the reference signal Fin was varied or the oscillation gain of the voltage control oscillator
101
was changed with manufacturing variations.
If, moreover, the components of capacitors and resistors used in the low-pass filter
104
are built in an LSI (large scale integrated circuit), a very large area is needed and, in this case, the manufacturing variations of the components have to be taken into consideration. On the other hand, if the components of capacitors and resistors are mounted externally, a special-purpose terminal is required. Thus, the low-pass filter
104
is an obstacle to miniaturization of the N multiplier.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a frequency multiplier which is capable of generating an unregulated, stable multiple output without feedback control and which can be decreased in size.
In order to attain the above object, a frequency multiplier according to a first aspect of the present invention comprises a first delay circuit including a plurality of delay cells connected in cascade, each of the delay cells varying a delay amount between input and output signals in response to a first control signal, and a first one of the delay cells being supplied with a reference signal; a second delay circuit including a plurality of delay cells connected in cascade, each of the delay cells varying a delay amount between input and output signals in response to a second control signal, and a first one of the delay cells being supplied with an inverted signal of the reference signal; and an adder circuit for adding an output signal of the first delay circuit and an output signal of the second delay circuit together to generate a multiple signal of the reference signal.
A frequency multiplier according to a second aspect of the present invention comprises a first delay circuit having a plurality of delay circuit sections connected in cascade, a first one of the delay circuit sections being supplied with a reference signal, each of the delay circuit sections including; a delay cell in which a delay amount between input and output signals is varied substantially at a fixed rate in response to a first switching signal; a first level detection circuit having a first input terminal supplied with a first control signal and a second input terminal supplied with an output signal of the delay cell, for detecting a level of the output signal of the delay cell at a timing corresponding to one of rising and falling edges of the first control signal; and a switching circuit for generating the first switching signal based on a detection result of the first level detection circuit and the first control signal, and supplying the first switching signal to the delay cell; a second delay circuit having a plurality of delay circuit sections connected in cascade, a first one of the delay circuit sections being supplied with an inverted signal of the reference signal, each of the delay circuit sections including; a delay cell in which a delay amount between input and output signals is varied substantially at a fixed rate in response to a second switching signal; a second level detection circuit having a first input terminal supplied with a second control signal and a second input terminal supplied with an output signal of the delay cell, for detecting a level of the output signal of the delay cell at a timing corresponding to one of rising and falling edges of the second control signal; and a switching circuit for generating the second switching signal based on a detection result of the second level detection circuit and the second control signal, and supplying the second switching signal to the delay cell; and an adder circuit for adding an output signal of the first delay circuit and an output signal of the second delay circuit together to generate a multiple signal of the reference signal.
According to the frequency multiplier of the present invention, a multiple output can be generated only by propagating a reference signal through a delay circuit, without any parts such as capacitors and resistors for low-pass filters or without feedback control.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 5297179 (1994-03-01), Tatsumi
patent: 5530387 (1996-06-01), Kim
patent: 5587673 (1996-12-01), MacDonald
patent: 6091271 (2000-07-01), Pant et al.

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