Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
1999-12-03
2001-01-16
Vu, David (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169100, C345S067000, C345S068000
Reexamination Certificate
active
06175194
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for driving a plasma display panel (hereinafter, referred to as PDP) of a matrix display system.
2. Description of the Related Art
In recent years, a thin display apparatus has been requested in association with the increase in size of a display apparatus and various thin display apparatuses have been put into practical use. Attention is paid to an AC (alternating current discharge) type PDP as one type of the thin display apparatuses.
The PDP has a plurality of column electrodes (address electrodes) and a plurality of row electrodes arranged so as to intersect the column electrodes. Each of the row electrode pairs and the column electrodes are covered by a dielectric layer against a discharge space and have a structure such that a discharge cell corresponding to one pixel is formed at an intersecting point of the row electrode pair and the column electrode. Since the PDP provides a light emission display by using a discharge phenomenon, each of the discharge cells has only two states: a state where the light emission is performed and a state where it is not performed. A sub-field method is used to provide a halftone luminance display by the PDP. In the sub-field method, a display period of one field is divided into N sub-fields, a light emitting period having a duration period corresponding to a weight of each bit digit of the pixel data (N bits) is allocated every sub-field, and the light emission driving is performed.
FIG. 1
is a diagram showing a schematic construction of a plasma display apparatus for performing the halftone luminance display by using the sub-field method.
In
FIG. 1
, a driving apparatus
100
converts a supplied video signal into digital pixel data corresponding to each pixel, applies pixel data pulses corresponding to the pixel data to column electrodes D
1
to D
m
of a PDP
10
. The driving apparatus
100
applies various driving pulses as will be explained as follows to row electrodes X
1
to X
n
and Y
1
to Y
n
, thereby performing a light emission drive control. One pair of row electrodes X and Y constitutes one row of the PDP
10
and is formed so as to intersect each of the column electrodes D
1
to D
m
. The column electrodes and the row electrode pairs are formed so as to sandwich a dielectric material (not shown). One pixel cell is formed in a portion where a set of column electrode and row electrode pair cross.
FIG. 2
is a diagram showing an example of a light emission driving format in one field period by the driving apparatus
100
.
As shown in
FIG. 2
, the display period of one field is divided into four sub-fields SF
1
to SF
4
. In each sub-field, an all-resetting step R
c
, a pixel data writing step W
c
, a light emission sustaining step I
c
, and an erasing step E are executed, respectively.
FIG. 3
is a timing diagram (in one sub-field) of various driving pulses which are applied at each step from the driving apparatus
100
to the column electrodes and row electrode pairs of the PDP
10
, respectively.
First, in the all-resetting step R
c
, the driving apparatus
100
simultaneously applies a reset pulse RP
x
of a negative polarity and a reset pulse RP
y
of a positive polarity as shown in
FIG. 3
to the row electrodes X
1
to X
n
and Y
1
to Y
n
, respectively. In response to the applied reset pulses RP
X
and RP
Y
, all of the discharge cells in the PDP
10
are reset-discharged and a predetermined amount of wall charges are uniformly formed in each discharge cell. All of the discharge cells, thus, are once initially set to “light emitting cells”.
In the next pixel data writing step W
c
, the driving apparatus
100
sequentially applies a pixel data pulse group DP
1
to DP
n
of each row to the column electrodes D
1
to D
m
at a predetermined scanning pulse period T
a
as shown in FIG.
3
. For example, in the pixel data writing step W
c
of the sub-field SF
1
, only the first bit is extracted from each of the input pixel data corresponding to each one of all of the discharge cells of the PDP
10
and the pixel data pulse group DP according to the logic level of the first bit is sequentially applied to the column electrodes D
1
to D
m
every row. In the sub-field SF
2
, only the second bit is extracted from each of the input pixel data corresponding to each of all discharge cells of the PDP
10
and the pixel data pulse group DP according to the logic level of the second bit is sequentially applied to the column electrodes D
1
to D
m
every row. Further, the driving apparatus
100
sequentially applies scanning pulses SP of a negative polarity as shown in
FIG. 3
to the row electrodes Y
1
to Y
n
at the scanning pulse period at the same timing as each applying timing of the pixel data pulse group DP. A discharge (selective erasure discharge) occurs in only the discharge cell in the intersecting portion of the “row” to which the scanning pulse SP was applied and the “column” to which the pixel data pulse of a high voltage was applied. The wall charges remaining in the discharge cell are selectively erased. By the selective erasure discharge, the discharge cell which was initialized to the state of the “light emitting cell” in the all-resetting step R
c
is shifted to the “non-light emitting cell”. The selective erasure discharge is not caused in the discharge cell to which the pixel data pulse of a low voltage was applied simultaneously with the scanning pulse SP and the state where it is initialized in the all-resetting step, namely, the state of the “light emitting cell” is maintained. The driving apparatus
100
applies a priming pulse PP of a positive polarity as shown in
FIG. 3
to the row electrodes Y
1
to Y
n
just before each scanning pulse SP is applied to each row electrode Y. A priming discharge occurs every row in response to the priming pulse PP applied. By the priming discharge, the charged particles which were reduced with the elapse of time although they had been obtained by the all-resetting operation are again formed in the discharge space of the PDP
10
. Since the scanning pulse SP is applied just after the charged particles were again formed, therefore, the selective erasure discharge is certainly caused and the erroneous writing of the pixel data is prevented.
In the light emission sustaining step I
c
, subsequently, the driving apparatus
100
repetitively applies a sustaining pulse IP
X
of a positive polarity as shown in
FIG. 3
to the row electrodes X
1
to X
n
at a predetermined sustaining pulse period T
s
. Further, the driving apparatus
100
repetitively applies a sustaining pulse IP
Y
of a positive polarity as shown in
FIG. 3
to the row electrodes Y
1
to Y
n
at the predetermined sustaining pulse period T
s
for a period of time during which the sustaining pulse IP
X
is not applied to the row electrodes X
1
to X
n
. The number of times (period) of applying the sustaining pulses IP
X
and IP
Y
in each sub-field is set in correspondence to the weight of each sub-field.
For example, as shown in
FIG. 2
, the sustaining pulses IP
X
and IP
Y
are applied by only the number shown by the following ratios of the number of times (period) in each of the sub-fields SF
1
to SF
4
.
SF
1
:
1
SF
2
:
2
SF
3
:
4
SF
4
:
8
After completion of the pixel data writing step W
c
, the discharge cells in which the wall charges remain, namely, only the “light emitting cells” discharge-emit the light each time the sustaining pulses IP
X
and IP
Y
are alternately applied. That is, in the pixel data writing step W
c
, only the discharge cells set to the “light emitting cells” repeat the flickering operation for only the number of times (period) as mentioned above and maintain the light emitting state.
In the erasing step E, subsequently, the driving apparatus
100
applies the erasing pulse EP as shown in
FIG. 3
to the row electrodes X
1
to X
n
, thereby allowing all of the discharge cells to be erasure-discharged at the same time and erasing the wall charges remaining in each discharge cell.
By executing the dri
Saegusa Nobuhiko
Tokunaga Tsutomu
Pioneer Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Vu David
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