Data processing device with data buffer control

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Details

3642613, 3642617, 3642631, 364244, 3642643, G06F 906, G06F 930, G06F 932

Patent

active

049929321

ABSTRACT:
A data processing device having a buffer for prefetching a plurality of instructions. The buffer is constructed by including two switching areas and one common area connecting to one of the two switching areas. An unconnected switching area of the two switching areas is used exclusively for prefetching a destination instruction of a conditional jump instruction, so that the destination instruction is prefetched to the unconnected switching area by a switching operation. Thus flexibility is increased, when the jump instructions are continued. Further, a number of prefetching destination instructions is determined so that a bottleneck in an instruction process is avoided, and thus the capacity of the two switching areas is reduced the hardware scale is not enlarged.

REFERENCES:
patent: 3401376 (1968-09-01), Barnes
patent: 3551895 (1970-12-01), Driscoll
patent: 3924245 (1975-12-01), Eaton et al.
patent: 4583163 (1986-04-01), Kobayashi

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