Amplifiers – With semiconductor amplifying device – Including gain control means
Reexamination Certificate
1997-02-26
2001-03-27
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including gain control means
C330S281000, C330S134000
Reexamination Certificate
active
06208209
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic gain control circuit which is likely to be integrated on the same chip as mixed (analog and digital) signal processing circuits.
2. Discussion of the Related Art
FIG. 1
shows a conventional automatic gain control circuit. It includes a variable gain amplifier
10
having a gain control input G. The gain of amplifier
10
is set by the voltage applied to the control input G. Often, especially in noisy environments, the input signal Vin to amplifier
10
and the gain control input G are differential.
An automatic gain control loop includes a peak detector
12
receiving the output Vout of amplifier
10
, and an integrator
13
which receives the output of peak detector
12
and controls the gain of amplifier
10
.
The integrator could have a differential output for driving the differential control input G of amplifier
10
. However, such a differential integrator would need at least one high value integrating capacitor having both its terminals connected to variable signals. This high value capacitor is usually not integrable, whereby an integrated circuit including the automatic gain control circuit would need two additional pins for connecting the high value capacitor externally.
With the type of integrator shown in
FIG. 1
, the integrated circuit only needs one pin
14
for connecting the external integrating capacitor C. The integrator shown includes a transconductance amplifier
16
receiving the output of peak detector
12
on a non-inverting input (+) and receiving a reference voltage Vref
1
on an inverting input (−). The output of the transconductance amplifier
16
is connected to a first terminal of capacitor C through pin
14
and to an inverting terminal g− of the differential gain control input of amplifier
10
. The non-inverting terminal g+ of the gain control input receives a constant reference voltage Vref
2
. The other terminal of capacitor C is connected to an analog ground AGND.
Usually, the automatic gain control circuit of
FIG. 1
is integrated on the same chip as digital circuits
18
which, for example, carry out a digital processing of the output Vout of amplifier
10
. These digital circuits have a digital ground DGND which is in principle not connected to the analog ground AGND. However, digital noise caused by the high frequencies used in the digital circuits
18
, inevitably couples into the analog ground AGND. This digital noise affects the gain control input G of amplifier
10
through capacitor C and causes distortion of the output signal Vout.
Capacitor C happens to be the only path through which the digital noise can affect the circuit. Any other path coupled to ground has noise canceling abilities. For example, the digital noise in the power supply lines (not shown) is canceled by the power-supply rejection ratio (PSRR) of amplifiers
10
and
16
. The reference voltages Vref
1
and Vref
2
are provided by low-noise voltage sources (not shown), which can be considered as not coupled to ground.
One solution to avoid digital noise affecting the circuit would be to use an integrator
13
with a differential output for driving the gain control input G of amplifier
10
in differential mode. However, as previously explained, the external capacitor C would have to be connected by two integrated circuit pins instead of only one.
Another solution would be to connect capacitor C to a low impedance low-noise voltage source, instead of to ground AGND. Here, two pins would again be necessary for connecting external capacitor C.
SUMMARY OF THE INVENTION
An object of the invention is to provide an automatic gain control circuit which is affected little by digital noise coupled through ground, while having only one pin for connecting an external integrating capacitor.
To achieve this object, the present invention provides an automatic gain control circuit comprising a variable gain amplifier having two differential gain control terminals, a first of said gain control terminals being connected to a constant reference voltage, a peak detector connected to the output of the variable gain amplifier and an integrator connected between the output of the peak detector and the second differential gain control terminal. The circuit further includes an integrating capacitor coupled to a ground terminal; and a second capacitor connected between the two differential gain control terminals.
According to an embodiment of the present invention, the second capacitor is integrated with the automatic gain control circuit on a same chip.
According to an embodiment of the present invention, the integrator includes a transconductance amplifier whose output is connected to said integrating capacitor and to the second differential gain control terminal.
According to another embodiment of the present invention, an automatic gain control circuit is disclosed, comprising a variable gain amplifier having first and second differential gain control terminals, the first differential gain control terminal being coupled to a constant reference voltage, a peak detector coupled to an output of the variable gain amplifier and an integrator coupled between an output of the peak detector and a ground terminal, and having an output coupled to the second differential gain control terminal. The invention further comprises means for minimizing noise from the ground terminal coupled between the first and second differential gain control terminals. The minimizing means comprises a first capacitor having a first terminal connected to the first differential gain control terminal and a second terminal connected to the send differential gain control terminal. The integrator includes an amplifier having an output coupled to the output of the integrator and an input coupled to the output of the peak detector, and a second capacitor coupled between the ground terminal and the output of the amplifier. The first capacitor is integrated on a same chip as the automatic gain control circuit.
According to another embodiment of the present invention, a method of minimizing noise in an automatic gain control circuit is disclosed, the method comprising amplifying an input signal in accordance with first and second differential gain control signals and outputting an amplified signal, detecting peaks of the amplified signal and outputting a peak signal, integrating the peak signal to provide the first differential gain control signal and minimizing noise in the first differential gain control signal by capacitively coupling the first differential gain control signal to the second differential gain control signal. The minimizing step comprises equalizing noise in the second differential gain control signal with the noise in the first differential gain control signal.
In another embodiment of the present invention, an automatic gain control circuit is disclosed, comprising a variable gain amplifier having an input, an output and first and second differential gain control terminals, an integrator coupled between the output of the variable gain amplifier and the first differential gain control terminal and means for coupling high frequency noise on the first differential gain control terminal to the second differential gain control terminal. The coupling means comprises a first capacitor having a first terminal coupled to the first differential gain control terminal and a second terminal coupled to the second differential gain control terminal.
REFERENCES:
patent: 4145665 (1979-03-01), Wisotzky et al.
patent: 4318053 (1982-03-01), Sondermeyer
patent: 4371842 (1983-02-01), Lee
patent: 4451797 (1984-05-01), Bains, Jr.
patent: 5309115 (1994-05-01), Hashimoto et al.
patent: 5418494 (1995-05-01), Betti et al.
patent: 5422602 (1995-06-01), Werrbach
patent: 5477191 (1995-12-01), Demicheli
Lewkowicz, J. and O'Day, R. L. Automatic Gain Control with Equalizer:, IBM Tech. Disc. Bull. vol. 21, No. 9, Feb.1979 pp. 3569-3570.
French Search Report from French Patent Application No. 96 02783, filed Feb. 29,
Galanthay Theodore E.
Morris James H.
Mottola Steven J.
SGS-Thompson Microelectronics Pte. Ltd.
Wolf Greenfield & Sacks P.C.
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