Structure for reducing cross-talk in VLSI circuits and...

Details Structure for reducing cross-talk in VLSI circuits and... Structure for reducing cross-talk in VLSI circuits and...

1998-07-14

2001-04-17

Gaffin, Jeffrey (Department: 2841)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C361S792000, C361S794000

Reexamination Certificate

active

06218631

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to VLSI circuits, and, more particularly, to an arrangement for reducing cross-talk between and within metal planes of such circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are continually being built and interconnected in denser and more complex packages. These circuits are being used to address high technology electronic applications and often include circuits that are designed to operate at high frequencies and at relatively high power levels. For example, many high performance digital computers are being implemented using VLSI (
v
ery
l
arge
s
cale
i
ntegration) circuits.
When used in a relatively dense electronic package, this type of circuitry must meet rigidly defined electrical and mechanical specifications. These specifications include line impedance, continuity, and minimal noise and cross-talk (cross-coupling) interferences.
Increasing device density has led to a decrease in the spacing between adjacent metal lines. Therefore, in deep-submicron technologies, cross-talk between parallel wires in the same wiring plane and between planes becomes increasingly important.
As metal lines are formed closer together, the potential for such capacitive and inductive interference between the lines increases. This interference is particularly troublesome when high frequency signals are propagated over adjacent lines in respective signal channels. The reliability of the electrical communication is thus reduced because the cross-talk acts as a source of noise which may introduce error in the communication.
Typically, adjacent wiring planes preferably have non-parallel wiring directions which reduces cross-talk to a negligible amount. However, planes i and i+2, i.e., a plane and the next but one plane, typically run in parallel direction and could generate cross-coupling.
BACKGROUND ART
In the prior art, this problem has been dealt with by constructing a metal line that is partially or totally shielded by a metal structure surrounding the metal line. A varying signal is propagated along the metal line, and the metal structure is coupled to ground potential. In combination, the two lines produce a negligible external electromagnetic field while also having a negligible susceptibility to external fields from adjacent lines. Examples of these prior art structures are, e.g., given in U.S. Pat. Nos. 3,560,893; 4,575,700; 3,370,184; 4,581,291 and 3,351,816.
Other prior art structures which have been designed to interconnect components of high performance digital computers, have included multiple layers consisting of conductors disposed in a polymer matrix. Those prior art structures have dielectric properties that allow high speed pulse propagation, but fail to significantly reduce the cross-talk of high speed signals in a highly dense electronic package.
Still other types of prior art structures include particularly selected shapes, materials, widths and thicknesses to implement the various planes comprising the structure. These prior art structures, however, have been unable to provide adequate high frequency and controlled impedance operation while sufficiently minimizing cross-talk.
U.S. Pat. No. 5,184,210 discloses an arrangement for interconnecting high density signals of integrated circuits having at least three layers. These layers comprise a signal layer for carrying signals in the electronic circuit, a dielectric layer of organic material disposed adjacent the signal layer, and a metallic reference layer. The layers are disposed such that the dielectric layer is arranged between the signal layer and the metallic reference layer. For providing controlled line impedance and for reducing cross-talk between the signals carried in the electronic circuit, the metallic reference layer includes uniformly spaced apertures which are situated in a slanted grid arrangement. Though cross-talk can be reduced by this structure, this solution is expensive and, what is even more disadvantageous, wastes a lot of space that could be used for additional wiring.
OBJECTS OF THE INVENTION
It is thus an object of the invention to provide a structure for reducing cross-talk in VLSI chips between parallel wires in the same plane and between planes.
It is another object of the invention to provide such a structure without wasting any space for additional wiring.
It is still another object of the invention to generate additional power routes where they are needed after wiring of the design.
It is still a further object of the present invention to provide a method for manufacturing the above mentioned structure.
These and other objects are accomplished by the structures described in claims
1
and
9
as well as by the method disclosed in claim
7
.
Advantageous embodiments are laid down in the dependent claims.
SUMMARY OF THE INVENTION
As already mentioned above, in a VLSI chip, planes i and i+2 typically run in parallel direction and therefore can create cross-coupling. This cross-coupling between planes i and i+2 is negligible if shielded by wiring on layer i+1. There are dense areas on a chip where shielding by intermediate planes will always be assured, but there are also other areas, typically next to the borders of the chip, where this is not the case.
When integrating a custom or memory macro on a chip, the environment is not known in advance and it is uncertain whether internal macro wires in plane i will be shielded to chip interconnects in plane i+2 or not.
In order to reduce the loss of wirability to a minimum and at the same time improve the electrical properties of the circuit, the present invention proposes to fill voltage and/or ground (GND) metal lines in free and unused channels of VLSI chips and connect those efficiently to the regular power image.
Thus, vertical coupling between wiring layers (metal planes) i and i+2 is reduced nearly to zero. This applies to coupling both between internal macro wiring and chip level signal wiring. Furthermore, the clock skew due to different adjacencies for clock wires is reduced, since the clock line capacitance is constant as each adjacent channel is occupied by either signal or GND line.


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