Instruction address producing unit capable of accessing an instr

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3642551, 3642555, 3642558, 364247, 3642472, G06F 900

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active

048644935

ABSTRACT:
In an instruction address producing unit for producing an instruction address in response to an entry descriptor in cooperation with a segment descriptor segment (48), the entry descriptor has first and second segment fields (41 and 42) corresponding to first and second instruction descriptors stored in the segment descriptor segment, respectively. The first and the second instruction descriptors are partially read out of the segment descriptor segment to be kept in an instruction segment register (52) and an instruction counter (57), respectively, and to be produced as first and second retained instruction descriptors. An adder circuit (58) adds the first retained instruction descriptor to the second retained instruction descriptor to produce a result of addition as the instruction address. Each of the first and the second instruction descriptors may be an extended segment descriptor.

REFERENCES:
patent: 4050060 (1977-09-01), Birner et al.
patent: 4453212 (1984-06-01), Galther et al.
patent: 4466056 (1984-08-01), Tanahashi
patent: 4672558 (1987-06-01), Takawe

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