Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-04-01
2001-07-24
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S055000, C327S057000
Reexamination Certificate
active
06265907
ABSTRACT:
This invention concerns a type of signal transmission circuit. More specifically, this invention concerns a type of signal transmission circuit wherein the signal is amplified and transmitted by means of the positive feedback of an intermediate amplifier circuit having input/output shared terminals.
BACKGROUND OF THE INVENTION
Heretofore, TTL logic used to be the main type of general-purpose logic. However, in the recent years, CMOS logic has replaced the TTL logic as the main type.
The types of CMOS logic include standard CMOS logic (with a chip size about 20 mm and a transmission delay time about 80 nsec), high-speed CMOS logic (with the same chip size as above, and a transmission delay time about 15 nsec), new high-speed CMOS logic (with the same chip size and a transmission delay time about 8 nsec), and advanced high-speed CMOS logic (with the same chip size and a transmission delay time about 4 nsec).
In a conventional LSI chip, such as a CMOS circuit providing a signal transmission circuit, inverters may be used as a driver circuit and a receiver circuit.
FIGS. 10-13
show some examples of a conventional signal transmission circuit.
In the circuit shown in
FIG. 10
, driver circuit
50
using inverter
52
and receiver circuit
51
using inverter
53
are connected to each other by wiring
200
, and the signal is transmitted from driver circuit
50
to receiver circuit
51
by wiring
200
, so that the so-called rounding of the signal can be reduced.
In the circuits shown in
FIGS. 11-13
, in the case when the signal transmission time becomes longer as the signal transmission distance is increased so that the time constant RC due to parasitic resistance and capacitance of wiring
200
, corresponding to the delay in the signal transmission time, inverter
54
(FIG.
11
), inverters
55
,
56
(FIG.
12
), or inverters
57
-
59
(
FIG. 13
) are connected in series between driver circuit
50
and receiver circuit
51
to improve the delay of the signal transmission time. These inverters
54
-
59
act as an intermediate amplifier circuit, respectively.
FIG. 14
shows a diagram of characteristics illustrating the relationship between the power consumption of the conventional signal transmission circuit and the wiring length shown in
FIGS. 10-13
.
In this figure, curve OC in the case when no inverter is used as the intermediate amplifier circuit (the graph which shows the characteristics of the signal transmission circuit in
FIG. 10
) indicates that the power consumption is about 1.05 mW for a wiring length of 20×1000 &mgr;m (2 cm) in an LSI chip. In this case, the signal cycle time is 60 nsec, the wiring capacitance is 0.25 FF/1 &mgr;m, and there is a wiring resistance of 0.1 &OHgr;/square.
Curve
2
C in the case when inverter
54
is used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of
FIG. 11
) indicates that the power consumption is about 1.1 mW for a wiring length of 20×1000 &mgr;m. Curve
3
C in the case when inverters
55
,
56
are used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of
FIG. 12
) indicates that the power consumption is about 1.15 mW for a wiring length of 20×1000 &mgr;m. Curve
4
C in the case when inverters
57
-
59
are used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of
FIG. 13
) indicates that the power consumption is about 1.2 mW for a wiring length of 20×1000 &mgr;m.
That is, in the conventional signal transmission circuit, when the wiring length is kept constant such as 2 cm, as more inverters
54
-
59
are connected in series as intermediate amplifiers interposed in the wiring
200
(FIGS.
10
-
13
), the power consumption of the signal transmission circuit increases. When the signal transmission circuit without an inverter used as an intermediate amplifier as shown in
FIG. 10
is compared with the signal transmission circuit shown in
FIG. 13
with three inverters that are used as intermediate amplifiers, it can be seen that while the power consumption of the signal transmission circuit in
FIG. 10
is 1.05 mW, for the signal transmission circuit shown in
FIG. 13
, the power consumption is increased to 1.2 mW.
FIG. 15
shows the relationship between the wiring length and the delay in signal transmission.
FIGS. 10-13
show the simulation results.
In
FIG. 15
, the ordinate represents the delay, while the abscissa represents the wiring length.
For example, when the wiring length within LSI chip is 20×1000 &mgr;m (2 cm), curve OC in the case when no inverter is used as the intermediate amplifier circuit (the graph which shows the characteristics of the signal transmission circuit in
FIG. 10
) indicates a delay of about 5.5 nsec; curve
2
C in the case when inverter
54
is used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of
FIG. 11
) indicates a delay of about 5 nsec; curve
3
C in the case when inverters
55
,
56
are used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of
FIG. 12
) and curve
4
C in the case when inverters
57
-
59
are used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of
FIG. 13
) indicate a delay of about 4.5 nsec.
That is, in the conventional signal transmission circuit, when the wiring length is kept constant at 2 cm, as more inverters
54
-
59
are connected in series as intermediate amplifiers interposed in the wiring
200
(FIGS.
10
-
13
), the delay time becomes shorter. When the signal transmission circuit without an inverter used as an intermediate amplifier as shown in
FIG. 10
is compared with the signal transmission circuit shown in
FIG. 13
with three inverters that are used as intermediate amplifiers, it can be seen that while the delay of the signal transmission circuit in
FIG. 10
is about 5.5 nsec, for the signal transmission circuit shown in
FIG. 13
, the delay is shortened to 4.5 nsec.
As pointed out hereinbefore, in the aforementioned conventional example, when a number of inverters are connected as intermediate amplifiers so as to reduce the delay of the signal transmission, the power consumption is increased. This is a problem of contradiction. In addition, when the number of the inverters used as intermediate amplifiers is small, the power consumption is still high.Besides, when the number of the inverters used as intermediate amplifiers is increased, there is a limitation on the improvement of the delay of the signal transmission.
FIGS. 16 and 17
show specific circuit examples of other conventional signal transmission circuits designed for improving the aforementioned problems of a signal transmission circuit using inverter circuits.
In the signal transmission circuit shown in
FIG. 16
, driver circuit
60
and receiver circuit
61
are connected by a precharge circuit
62
.
Driver circuit
60
comprises CMOS inverters
63
,
64
, driving p-type MOS transistors
65
,
67
, and driving n-type MOS transistors
66
,
68
.
Input terminal IN is connected to the input of inverter
63
and the gate of nMOS transistor
68
; the output of inverter
63
is connected to the gate of pMOS transistor
65
. The voltage applied on input terminal IN is applied as the gate voltage on the gate of pMOS transistor
65
and the gate of nMOS transistor
68
, respectively.
The inverted input terminal N-IN is connected to the input of inverter
64
and the gate of nMOS transistor
66
, and the output of inverter
64
is connected to the gate of pMOS transistor
67
. The voltage applied on inverted input terminal N-IN is then applied as the gate voltage on the gate of pMOS transistor
67
and the gate of nMOS transistor
66
as the gate voltage.
The drain of nMOS transistor
66
is connected to the drain of pMOS transistor
65
to form a first transistor pair,
Cunningham Terry D.
Kempler William B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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