Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1999-09-08
2001-03-06
Young, Lee (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S852000, C257S773000, C257S758000
Reexamination Certificate
active
06195873
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and more particularly, to a method for decreasing contact resistance in a semiconductor device.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconductive substrate.
The conductive interconnections are typically accomplished through the formation of a plurality of conductive lines and conductive plugs, commonly referred to as contacts or vias, formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, polysilicon, etc. A contact is generally used to define an interconnection (e.g., using polysilicon or metal) to an underlying polysilicon layer, while a via denotes a metal to metal interconnection. In either case, a contact opening is formed in an insulating layer overlaying the conductive member. Typically, photoresist is deposited over the insulating layer and selectively patterned to define contact patterning regions. The exposed photoresist is removed, leaving a portion of the insulating layer exposed. The exposed portion of the insulating layer is then anisotropically etched to extend the opening to reach the underlying conductive member. A second conductive layer is then formed over the contact opening and electrical communication is established with the contact member.
The volume of the contact determines the contact resistance of the interconnection. A higher contact resistance correlates to a slower device. Commonly, the contact opening is defined smaller than the underlying conductive member to allow some overlay between the conductive member and the photoresist mask. Overlay as used herein refers to the degree to which the contact opening is aligned with the underlying conductive member. A good overlay is reflected in the contact opening being centered over the conductive member, while a less desirable overlay is skewed in one or more directions toward the edges of the conductive member. If the contact opening is misaligned, the contact may be formed sufficiently close to an adjacent device to interfere with its operation. Such a condition may require that the device be scrapped. Thus, there exists a trade-off between contact size (i.e., affects device speed) and acceptable overlay (i.e., affects defect count). If the contact area is increased, the propensity for defects is also increased.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for forming an electrical contact. A base layer having a conductive member is provided. An intermediate layer is formed over at least the conductive member. A photoresist layer is formed and patterned over at least a portion of the intermediate layer to define a contact patterning region above the conductive member. An amount of overlay between the contact patterning region and the conductive member is measured. A size of a contact opening is determined based on the amount of overlay. The contact opening of the determined size is formed in the intermediate layer. The contact opening communicates with the conductive member.
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patent: 6016011 (2000-01-01), Cao
patent: 6043151 (2000-03-01), Gonzalaz et al.
patent: 6064119 (2000-05-01), Jun et al.
patent: 6114244 (2000-09-01), Hirose
patent: 57-93568 (1982-06-01), None
patent: 3-276763 (1991-12-01), None
Advanced Micro Devices , Inc.
Smith Sean
Williams Morgan & Amerson P.C.
Young Lee
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