Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-01-29
2001-06-12
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C174S260000
Reexamination Certificate
active
06246015
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to semiconductor packaging, and more particularly, to a printed circuit board for use in a ball grid array semiconductor package that prevents the accumulation of an electrostatic charge in the package during molding, thereby preventing damage to the components in the package caused by a rapid discharge of such an electrostatic charge.
2. Description of the Related Art
The recent trend in consumer electronics has been toward smaller, lighter products having improved capabilities and capacities, which has, in turn, resulted in a demand for semiconductor chips that are smaller, more highly integrated, and of higher capacity. Accordingly, modem semiconductor packages must have excellent electrical characteristics, high heat dissipating capabilities, and a large input/output-terminal capacity, to enable such small, highly integrated, and efficient semiconductor chips to perform as expected.
Ball grid array (BGA) semiconductor packages have been proposed and widely used as an exemplary package capable of enabling small, efficient and highly integrated semiconductor chips to meet their design goals effectively. Such BGA packages are easily formed on a conventional printed circuit board (PCB) and can effectively reduce the overall length of electric circuits incorporating them. BGA packages also utilize power- and/or ground-bonding areas more effectively, thus yielding excellent electric characteristics. Also, the input/output terminal density of BGA packages is greater than that of conventional quad flat packages (QFPs), which better comports with the trend toward smaller, denser packages.
FIGS. 8
a
and
8
b
are top and bottom plan views, respectively, of a conventional, strip-type multiple-package PCB
10
typically used in the manufacture of BGA semiconductor packages.
FIG. 9
is a sectional view of a typical BGA semiconductor package incorporating such a conventional PCB.
As shown in the drawings, the typical PCB
10
′ comprises a dielectric substrate
11
, typically made of a thermosetting resin, e.g., a bismaleimidetriazine or polyimide resin. A plurality of conductive traces
12
are formed on each side of the substrate to form predetermined circuit patterns on each side of the board. A plurality of die, or chip mounting plates
16
are centrally provided on the top surface of the substrate
11
for the mounting of semiconductor chips thereon. A plurality of conductive via holes
13
are formed through the substrate
11
to electrically connect the conductive traces
12
of both sides of the PCB with each other. A plurality of solder ball lands
14
are electrically connected to the conductive traces
12
on the bottom surface of the substrate.
As shown in
FIG. 8
a
, a mold runner gate
17
, comprising a thin, conductive metal plate or plating of, e.g., gold or palladium, extends from a corner of the substrate
11
to the chip mounting plate
16
, and serves to guide molten molding compound, e.g., a resin, into the region of the chip mounting plate
16
during a package molding operation described in more detail below.
A non-conductive solder mask
15
coats both sides of the substrate
11
outside of selected areas of the conductive traces
12
, e.g., around the edge of the chip mounting plate
16
, and on the solder ball lands
14
, and serves to electrically isolate the traces
12
from each other and to protect them from harmful environmental elements.
The mold runner gate
17
is electrically connected on the PCB
10
′ to a ground ring
25
formed about the periphery of the chip mounting plate
16
by means of a conductive ground trace
22
. The grounded elements of a semiconductor chip (not shown in
FIG. 8
a
), typically ground pads, are electrically connected to the ground ring
25
by means of bonding wires
50
(see
FIG. 9
) that extend between the chip and the ground ring. In the BGA package, ground signals are applied from the semiconductor chip to the mold runner gate
17
, and the voltage drops occurring between the chip and ground can be easily and precisely measured. Likewise, any voltage drops occurring in the wire bonds between the chip and the conductive traces
12
can also be checked easily and precisely. The grounded mold runner gate/grounding ring arrangement therefore forms an effective common ground area for purposes of complete circuit definition within the BGA package.
As seen in
FIGS. 8
a
and
8
b
, tooling holes
18
are used in the strip-shaped PCB
10
to position and fix the PCB in a package molding tool assembly. Singularizing holes
19
are used as reference points during singularization, or separation, of the individual BGA packages from the multiple-package PCB
10
′, which is typically accomplished by die cutting. The dotted square
19
′ defined by the singularizing holes
19
corresponds to the line along which the PCB is cut when the individual BGA packages are separated from the plurality of simultaneously fabricated packages on the PCB
10
′.
FIG. 10
is a sectional view through the region around a via hole
13
of the PCB
10
′. As shown in the drawing, the via holes
13
are formed between conductive traces
12
on opposite sides of the board to interconnect them through the board. The interior wall of the via hole
13
is plated with a conductive metal, while the solder mask
15
overlays the top surface of the trace
12
and fills the void in the via hole
13
. A solder ball
80
is welded to the solder ball land
14
through an opening in the solder mask
15
and is used as an input/output terminal of the BGA package.
FIG. 11
is a sectional view through a tooling hole
18
, as taken along the line E′—E′ in
FIG. 8
b
.
FIG. 12
reveals that the tooling hole
18
is, like the via hole
13
, formed through the thickness of the substrate
11
of the PCB. However, unlike the via hole
13
, the tooling hole
18
does not include a conductive layer on its interior surface that electrically connects the upper and lower surfaces of the board, nor does the solder mask
15
fill the interior void of the hole.
A conventional BGA semiconductor package
1
that incorporates a conventional PCB
10
′ of the type described above is shown in elevational cross-section in FIG.
9
. Typically, a plurality of such packages are simultaneously fabricated on the PCB
10
′ in the following manner: First, a plurality of semiconductor chips
40
are mounted, typically by means of a bonding layer (not shown), on the strip-shaped PCB
10
′, one on each of the chip mounting plates
16
. Each chip
40
is then electrically connected to wire bonding areas on the conductive traces
12
(which are free of any solder masking
15
) using a plurality of fine, conductive bonding wires
50
.
After wire bonding is complete, a plurality of resin envelopes
70
are molded onto the upper surface of the PCB
10
around each of the chips
40
and its associated bonding wires
50
to individually encapsulate and protect them against damaging mechanical and electrical elements in their environment. After molding, a plurality of solder balls
80
, which function as the input and/or output terminals of the packages
1
, are respectively welded to the solder ball lands
14
. The solder ball welding step is followed by a singularizing step in which the simultaneously formed plurality of BGA packages
1
of a reduced, uniform size, are separated from the PCB
10
′, typically by die cutting, into individual BGA packages
1
of the type illustrated in FIG.
9
.
In the above manufacturing process, the molding procedure is carried out with the individual semiconductor chips
40
mounted on the PCB
10
′ and with the PCB clamped between top and bottom molds
30
a
and
30
b
, as shown in FIG.
12
. The encapsulating resin reinforces the delicate wires
50
and bonds them securely to both the associated chip
40
, the conductive traces
12
, and the upper surface of the PCB′
10
in a sealed, monolithi
Anam Semiconductor Inc.
Lawrence Don C.
Norris Jeremy
Paladini Albert W.
Skjerven Morrill & MacPherson LLP
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