Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2000-11-10
2001-06-19
Britton, Howard (Department: 2413)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C348S567000, C348S568000, C375S240210, C375S240250
Reexamination Certificate
active
06249547
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to video decoders and, more particularly, to methods and apparatus for implementing video decoders that are capable of decoding high definition television (“FDTV”) signals and/or standard definition television (“SDTV”) signals.
BACKGROUND OF THE INVENTION
The use of digital, as opposed to analog signals, for television broadcasts and the transmission of other types of video and audio signals has been proposed as a way of allowing improved picture quality and more efficient use of spectral bandwidth over that currently possible using analog NTSC television signals.
The International Standards Organization has set a standard for video data compression for generating a compressed digital data stream that is expected to be used for digital television. This standard is referred to as the ISO MPEG (International Standards Organization —Moving Picture Experts Group) (“MPEG”) standard. In accordance with the MPEG standard, video data is encoded using discrete cosine transform encoding and is arranged into variable length encoded data packets for transmission.
One version of the MPEG standard, MPEG-2, is described in the International Standards Organization—Moving Picture Experts Group, Drafts of Recommendation H.
262
, ISO/IEC 13818-1 and 13818-2 titled “Information Technology—Generic Coding Of Moving Pictures and Associated Audio” is (hereinafter “the November 1993 ISO-MPEG Committee draft”) hereby expressly incorporated by reference. Any references made in this patent application to MPEG video data is to be understood to refer to video data that complies with MPEG-2 standards as defined in the November 1993 ISO-MPEG Committee drafts.
MPEG video data may be used to support either high definition television (“HDTV”), wherein the video frames are of higher resolution than those used in present NTSC signals, or what will be referred to as standard definition television (“SDTV”), e.g., television which has approximately the same resolution per frame as the existing analog NTSC standard. Because HDTV, which includes the proposed United States Advanced Television Standard (“US ATV”), provides higher resolution than SDTV, more data is required to represent a HDTV frame than is required to represent a SDTV frame. Accordingly, it is possible to transmit multiple SDTV signals in the same bandwidth required to support a single HDTV signal.
MPEG Main Profile at Main Level (“MP@ML”) specifies various requirements for an MPEG compliant standard definition television signal and associated decoding equipment. MP@ML allows pictures as large as 720×576 pels for a total of 414,720 pels per picture. The proposed standard for US ATV allows for pictures as large as 1920×1080 pels for a total of 2,073,600 pels per picture.
Because of the relatively large amount of data required to represent each frame of a HDTV picture, HDTV decoders must support much higher data rates than SDTV decoders. The additional memory required by a HDTV decoder, as compared to a standard SDTV decoder, and the increased complexity associated with the inverse DCT circuit and other components of a HDTV decoder can make a HDTV decoder considerably more expensive than an SDTV decoder.
In fact, the cost of memory alone may make a HDTV set incorporating a HDTV decoder prohibitively expensive for some consumers. It is expected that a fully MPEG compliant video decoder for HDTV will require a minimum of 10 MB of RAM for frame storage with a practical HDTV decoder probably requiring about 16 MB of relatively expensive Synchronous DRAM.
Accordingly, there is a need for a method and apparatus that permits: (1) a simplification of the complexity of the circuitry required to implement a HDTV decoder, (2) a reduction in the amount of memory required to implement a HDTV decoder circuit, and (3) a single decoder that is capable of decoding both SDTV and HDTV signals. Furthermore, it is desirable that the cost of such a decoder be low enough that it is in a range that would be acceptable to most consumers, e.g., approximately the cost of a SDTV decoder.
While various proposals call for transmitting only US ATV signals it has also been suggested that some digital SDTV signals be broadcast. Various combinations of broadcasting HDTV and SDTV signals are possible with multiple SDTV shows being broadcast during a particular time of the day and a single HDTV broadcast being transmitted in the same bandwidth used for the SDTV signals at a different time of the day.
Thus, in order to remain compatible with both HDTV and SDTV broadcasts, there would be value in a television receiver include a video decoder capable of decoding both HDTV and SDTV signals and furthermore, that such a video decoder be capable of being implemented at a relatively low cost.
In addition, there is a need for a method and apparatus for implementing picture-in-picture capability in a digital television without incurring the cost of multiple full resolution decoders. In known analog picture-in-picture systems, during picture-in-picture operation, and full resolution decoder is normally used to decode the TV signal used to produce a main picture and a second full resolution decoder is used to decode the- television signal which is used to provide the second picture displayed within a small area of the main picture.
SUMMARY OF THE PRESENT INVENTION
The present invention is directed to video decoders and, more particularly, to methods and apparatus for implementing video decoders that are capable of decoding high definition television (“HDTV”) signals and/or standard definition compressed video signals.
In particular the present invention is directed to a plurality of methods and apparatus for reducing the complexity of digital video decoder circuitry and for reducing video decoder memory requirements. In accordance with the present invention, in order to reduce the cost associated with implementing a joint HD/SD television decoder, the decoder of the present invention is designed to optimize the amount of circuitry that is used during both HD and SD television decoder operation.
A HDTV decoder capable of decoding HDTV signals at less than full HDTV resolution, e.g., at approximately SDTV resolution and/or decoding SDTV signals is described. The decoder of the present invention can also be used to decode SDTV signals at full SD resolution. It is expected that as a result of the various data reduction features and circuit simplifications of the present invention a combined HDTV/SDTV decoder that outputs pictures at approximately SDTV resolution can be built at approximately 130% of the cost of a digital SDTV decoder.
In accordance with one embodiment of the present invention the described reduced resolution HDTV video decoders are used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without the use of multiple full resolution video decoders.
The decoder of the present invention achieves substantial reductions in circuit complexity and memory requirements through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating bytes of data representing pixel values so that the pixel values are represented using only 5, 6 or 7 bits as opposed to, e.g., 8 bits per DCT value.
In accordance with one embodiment of the present invention, the preparser is used to discard data to permit a smaller channel buffer than would otherwise be required to be used. In addition, the preparser discards run-length/amplitude symbols for each macroblock, e.g., the run-length/amplitude symbols for each luminance or chrominance block of a macroblock, when the number of run-length/amplitude symbols exceeds a maximum preselected number per macroblock and/or block. In one embodiment the preparser also limits the number of bits output per unit time period, e.g., by limiting the number of bits per macroblock, such that a predetermined data processing rate which is determined by the combined capability of the coded data buffer and syntax parser
Boyce Jill MacDonald
Pearlstein Larry
Britton Howard
Hitachi America Ltd.
Straub Michael P.
Straub & Pokotylo
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