Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1999-06-16
2001-08-28
Wong, Don (Department: 2821)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S724000, C438S106000, C438S107000, C438S455000
Reexamination Certificate
active
06281576
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronic semiconductor package interconnections, and more particularly to a method and structure for joining electronic semiconductor chip packages.
2. Description of Related Art
As semiconductor devices become smaller and denser, it becomes increasingly important to join two semiconductor parts together, i.e., chip to chip, or chip to substrate, to reduce delay and improve performance. While existing processes can be used to join semiconductor chips having large feature sizes to a substrate, current technology does not provide an adequate method to make extremely small solder connections which can be used at a very early back end of the line (“BEOL”) levels and later wiring levels. Controlled collapse chip connection (“C4”) technology can be employed for first level assembly of chips on ceramic carriers, as disclosed in U.S. Pat. No. 5,729,896. However, C4 technology and ball limiting metallurgy is for much larger scale connections and feature sizes, rather than the micro connections of the present invention.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and structure to join semiconductor parts together.
Another object of the present invention is to provide a method and structure to join together semiconductor parts with extremely small electrical connections.
A further object of the present invention is to provide a method and structure to fabricate semiconductor chips and substrates separately and then join them together for functionality.
It is yet another object of the present invention to provide a method for joining multiple chips from different technologies together via a common back end for group functionality.
It is yet still another object of the present invention to provide a method and structure for joining semiconductor parts together which allows rework capability.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of electrically connecting electronic semiconductor components. The method comprises the steps of providing a first semiconductor substrate comprising a plurality of layers, at least one of the layers comprising a first electronic semiconductor component. The first semiconductor substrate preferably has at least one conductive column formed thereon, with the column being electrically connected to the first electronic semiconductor component. In the preferred embodiment the first semiconductor substrate comprises a first electrically insulating layer over the first electronic component, a first electrically conductive layer over the first insulating layer and a second electrically insulating layer over the first conductive layer. Preferably, the column is formed within the second insulating layer and electrically joined to the second conductive layer. In the preferred embodiment the first electronic semiconductor component comprises a first semiconductor layer with at least one front end of the line device comprising at least one semiconductor integrated circuit, and a second semiconductor layer with at least one partial back end of the line device. It is preferred that the second semiconductor layer have at least one electrically conductive stud extending therefrom, the stud being adapted to provide an electrical connection to the second semiconductor layer.
The method also includes providing a second semiconductor substrate comprising a plurality of layers, at least one of the layers comprising a second electronic semiconductor component. It is preferred that the second substrate have at least one via formed therein, the via be adapted to receive the column and provide an electrical connection to the second electronic semiconductor component. In the preferred embodiment the second semiconductor substrate comprises a third electrically insulating layer over the second electronic semiconductor component, a second electrically conductive layer over the third insulating layer, and a fourth electrically insulating layer over the second conductive layer. In the preferred embodiment, the second electronic semiconductor component comprises a back end of the line device and may be a wiring substrate. It is preferred that the via is formed in the fourth insulating layer.
The preferred method also comprises inserting the column into the via to join the first semiconductor substrate to the second semiconductor substrate and electrically connecting the first electronic semiconductor component to the second electronic semiconductor component.
In the preferred embodiment, the conductive column comprises a first layer of a conductive material covered by a layer of a heat flowable electrically conductive material having a lower melting point than the first layer of a conductive material. It is preferred that the first layer of conductive material is plated copper and the heat flowable conductive material is plated solder. In the preferred embodiment, the first electronic semiconductor component is electrically connected to the second electronic semiconductor component by heating the joined structure sufficiently to flow the heat flowable conductive material.
In another aspect, the present invention comprises a structure for electrically connecting electronic semiconductor components comprising a first semiconductor substrate having a plurality of layers, at least one of said layers comprising a first electronic semiconductor component. It is preferred that the first semiconductor substrate have at least one conductive column formed therein, the column being adapted to provide an electrical connection to said first electronic component. In the preferred embodiment the structure also includes a second semiconductor substrate having a plurality of layers, at least one of the layers comprising a second electronic semiconductor component. It is preferred that the second semiconductor substrate have at least one via formed therein, the via being adapted to receive the conductive column and provide an electrical connection to the second electronic semiconductor component.
In the preferred embodiment of the structure of the present invention, the first electronic semiconductor component comprises a first semiconductor layer with front end of the line devices and a second semiconductor layer with partial back end of the line devices built through a stud level. It is preferred that the first semiconductor substrate comprise a first electrically insulating layer over said first electronic component, a first electrically conductive layer over said first insulating layer; and a second electrically insulating layer over said first conductive layer, said second insulating layer having said columns formed therein. In the preferred embodiment of the structure of the present invention the second semiconductor substrate comprises a third electrically insulating layer over the second electronic component, a second electrically conductive layer over the third insulating layer; and a fourth electrically insulating layer over the second conductive layer, the fourth insulating layer having the via formed therein.
It is also preferred that in the structure of the present invention the conductive column comprise a layer of a heat flowable electrically conductive metal such as plated solder over a layer of an electrically conductive material such as plated copper. In the preferred embodiment the heat flowable conductive metal has a lower melting point than the layer of a conductive material.
In the preferred embodiment of the structure of the present invention the column is electrically joined to the second conductive layer.
REFERENCES:
patent: 4794092 (1988-12-01), Solomon
patent: 4797508 (1989-01-01), Chant
patent: 4853277 (1989-08-01), Chant
patent: 5286335 (1994-02-01), Drabik et al.
patent: 5663101 (1997-09-01), Cronin
patent: 5729896 (1998-03-01
Hakey Mark C.
Hsioh-Lien Ma William
DeLio & Peterson LLC
International Business Machines - Corporation
Peterson Peter W.
Sabo William D.
Vo Tuyet T.
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