Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
1998-11-17
2001-04-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S457000, C438S938000, C438S962000
Reexamination Certificate
active
06221739
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the fabrication of non-planar semiconductors, and more particularly to a method for bonding single crystal membranes to a curved surface and relieving the lattice stress in the membranes due to formation of quantum wires of a dissimilar element.
1. Discussion of Related Art
In the microelectronic industry, integrated circuitry is typically fabricated on the surface of a flat single-crystal silicon wafer, generally known as a substrate, for use in microelectronic devices. Quality and characteristics of these microelectronic devices are altered by quality and characteristics of the substrate. In particular, material purity, dislocation density, and level of lattice strain effect the behavior and performance of these devices. Additionally, the introduction of well controlled strain facilitates band-gap engineering and has led to the development of new devices, such as SiGe heterojunction bipolar transistors (HBT's), among others. Another trend in device engineering is associated with developing technology capable of producing low-dimensional structures, such as quantum wells, quantum wires and quantum dots.
Process induced lattice stress (as a result of oxidation, doping, ion implantation, silicidation, etc.) combined with the intrinsic silicon wafer dislocation density may significantly degrade device performance reliability. U.S. Pat. No. 4,769,689 discloses relieving the stress and resultant warping caused by lattice mismatch by doping germanium on an initial silicon crystal layer which consequently maintains the wafer in a flat configuration.
U.S. Pat. No. 5,546,417 discloses a basic semiconductor element having electronic circuitry fabricated on the surface of a non-planar substrate. The required non-planar nature of the basic semiconductor element assembly creates difficulties when integrating the silicon membrane with the non-planar supporting structure because stress may occur within the silicon lattice if the surface area of the supporting structure is a cylinder or cone having a small radius of curvature.
Furthermore, a high quality bond between the semiconductor material and the supporting structure is required. However, a problem arises while attempting to bond a flat silicon membrane to a non-planar supporting structure which has a small radius of curvature due to stress build-up within the membrane followed by lattice relaxation and resultant nucleation of dislocations. Such behavior prevents production of a semiconductor material having a sufficiently high quality for use in certain applications. Another challenge is in achieving a high quality bond between the supporting structure and a single crystal membrane.
Accordingly, it is an object of the present invention to provide a method of fabricating a substrate for a basic semiconductor element which overcomes these and other shortcomings in the prior art.
BRIEF SUMMARY OF THE INVENTION
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a method of fabricating single crystalline substrates conformed to supporting non-planar structures. The method can be implemented for conforming many classes of single crystalline materials (i.e. semiconducting, optical, magnetic, etc.) available in membrane form, to cylindrical or conical surfaces. In accordance with one aspect of the present invention, the method includes providing a thin semiconductor membrane and a non-planar supporting structure. The semiconductor membrane has a generally flat profile and comprises a single crystalline material. A semiconducting material having a different lattice constant but the same valence as the material of the membrane (e.g. an element from the same group of the Periodic Table or isovalent) is deposited onto the single crystal semiconducting membrane. The semiconducting membrane is positioned onto the non-planar supporting structure. The atoms of this isovalent element are incorporated into the crystal lattice of the host semiconducting membrane along the lines of maximum lattice strain. This enables the semiconducting membrane to bend and conform to the non-planar surface of the supporting structure, thereby relieving the lattice stress which, otherwise, would be present as a result of bending the membrane.
In accordance with one aspect of the present invention, after relieving the lattice strain by nucleation of isovalent material in the locations characterized by the largest strain, the bent semiconducting membrane is fused with the material of a supporting structure to form a substrate for the basic semiconductor element.
In accordance with another aspect of the present invention, the membrane containing the regular spaced lines of the isovalent material can be released from the support to form the flat wafer with equally spaced quantum wires.
In accordance with another aspect of the present invention, the method includes segmenting a unitary wafer of semiconductor material into a plurality of semi-attached wafer segments with each of the semi-attached wafer segments connected by a wafer bridge to an adjacent semi-attached wafer segment. A supporting structure is aligned with each of the semi-attached wafer segments and then the wafer segments are detached from each other by severing each of the wafer bridges. Each of the detached wafer segments are then bonded to one of the supporting structures, thereby forming a semiconductor element assembly.
REFERENCES:
patent: 3441742 (1969-04-01), Bevis
patent: 3562582 (1971-02-01), Broyles
patent: 3683296 (1972-08-01), Scalise
patent: 3711789 (1973-01-01), Dierschke
patent: 3875404 (1975-04-01), Fletcher et al.
patent: 4063083 (1977-12-01), Cathey et al.
patent: 4499607 (1985-02-01), Higgins
patent: 4499608 (1985-02-01), Broockman et al.
patent: 4551787 (1985-11-01), Mittal et al.
patent: 4564866 (1986-01-01), Comberg
patent: 4590538 (1986-05-01), Cray, Jr.
patent: 4662714 (1987-05-01), Mori
patent: 4682323 (1987-07-01), Corfield et al.
patent: 4755681 (1988-07-01), Oka et al.
patent: 4838630 (1989-06-01), Jannson et al.
patent: 4841355 (1989-06-01), Parks
patent: 4850044 (1989-07-01), Block et al.
patent: 4851856 (1989-07-01), Altoz
patent: 4893025 (1990-01-01), Lee
patent: 5067792 (1991-11-01), Lloyd
patent: 5111280 (1992-05-01), Iversen
patent: 5113403 (1992-05-01), Block et al.
patent: 5113404 (1992-05-01), Gaebe et al.
patent: 5238531 (1993-08-01), Macomber et al.
patent: 5361272 (1994-11-01), Gorelik
patent: 5546417 (1996-08-01), Gorelik
patent: 0176288 (1985-09-01), None
patent: 1-293589 (1989-11-01), None
Scifres et al., “Semiconductor Laser with Integral Light Intensity Detector”, Appl. Phys. Lett 35(1) Jul. 1, 1979, pp. 16-18.
Fourson George
Pham Thanh V
Thomas Kayden Horstemeyer & Risley
LandOfFree
Method for bonding single crystal membranes to a curved surface does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for bonding single crystal membranes to a curved surface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for bonding single crystal membranes to a curved surface will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2484788