Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
1998-12-18
2001-09-04
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S692000
Reexamination Certificate
active
06284560
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method for producing co-planar surface structures. More particular, the invention relates to a method for producing co-planar surface structures which are used as a basis for the formation of additional structural elements having flat surfaces over a wide range.
BACKGROUND OF THE INVENTION
Advances in micromachining technology have given rise to a variety of Micro-electromechanical systems (MEMS) including light modulators for low cost display applications. Such modulators provide high-resolution, high operating speeds (kHz frame rates), multiple gray scale levels, color adaptability, high contrast ratio, and compatibility with VLSI technology. One such modulator has been disclosed in U.S. Pat. No. 5,311,360, issued May 10, 1994 to Bloom et al., entitled “Method and Apparatus for Modulating a Light Beam”. This modulator is a micromachined reflective phase grating. It consists of a plurality of equally spaced deformable elements in the form of beams suspended at both ends above a substrate thereby forming a grating. The deformable elements have a metallic layer that serves both as an electrode, and as reflective surface for incident light. The substrate is also reflective and contains a separate electrode. The disclosure in U.S. Pat. No. 5,311,360 is silent about the efficiency decrease of the device if not all the beams of the device do not have a completely flat surface and the same cross section.
As disclosed in U.S. Ser. No. 90/216,202, entitled “Process for Manufacturing an Electro-Mechanical Grating Device,” chemical mechanical planarization can be used to advantageously accomplish the requirements of such a device namely; all the beams to have an optically flat surface, the same cross-section and a well defined beam to substrate distance, elimination of surface topography resulting in higher photo and dry etch yields as well as removing step coverage concerns.
Chemical mechanical polishing (CMP) has become a key technology as currently practiced in the semiconductor art for the planarization of metals and dielectrics and as taught in numerous U.S. patents such as that by Chow et al., U.S. Pat. No. 4,789,648, Carr et al., U.S. Pat. No. 4,954,142, and Beyer et al., U.S. Pat. No. 4,944,836. CMP provides full wafer planarization without additional masking or coating steps.
The use of CMP is also disclosed in U.S. Pat. No. 5,804,084, issued Sep. 8, 1998 to Nasby et al., entitled “Use of Chemical Mechanical Polishing In Micromachining”. The process suggested therein is for removing topography effects during fabrication of micromachines. A sacrificial oxide layer is deposited over a level containing functional elements (driving gear, liquid pump, etc.) with etched valleys between the elements such that the sacrificial layer has sufficient thickness to fill the valleys and extend thickness upwards to an extent that the lowest point on the upper surface of the oxide layer is at least as high as the top surface of the functional elements in the covered level. The sacrificial oxide layer is then polished down and planarized by CMP. Another level of functional elements is formed upon the new planarized surface. The teaching of his document does not provide a technique or a method how to get coplanar surfaces with the a CMP method. U.S. Pat. No. 5,804,084 shows only a method which can bring a plurality of islands existing in one layer to a single level. There is no need to consider a dishing effect which happens during the production of two coplanar surfaces.
However many of the micromachined structures typically fall into the regime of wide (>10 &mgr;m wide) recesses and sparsely populated structures. One of the difficulties encountered with CMP planarization is the “dishing” effect, which occurs in the planarization of wide recesses (i.e., usually >10 &mgr;m wide). The “dishing” effect during planarization results in thinning of the overfill layer in wide recesses resulting in a non-planar surface. The polish rate is affected by the topology of the surrounding areas with dishing becoming worse in sparsely populated regions. Dishing problems therefore present a severe manufacturing constraint in micromachining.
The dishing phenomenon is illustrated by reference to the schematic cross-sectional diagrams of
FIG. 1
a
and
FIG. 1
b
. Shown in
FIG. 1
a
is a substrate
10
onto which a first layer
15
is deposited. A narrow recess
11
and the wide recess
12
are shown formed in the first layer
15
. The surface of the first layer will contain small areas
13
between recesses and large areas
14
between recesses. Deposited over the first layer
15
and into both the narrow recess
11
and the wide recess
12
is a blanket conformal fill layer
20
. Shown in
FIG. 1
b
is the results of planarizing through a conventional CMP planarization method the blanket conformal fill layer
20
as illustrated in
FIG. 1
a
. As shown in
FIG. 1
b
, the surface of the planarized filled recess
22
is substantially dished in comparison with the surface of planarized filled recess
21
. There is also shown in
FIG. 1
b
the presence of a fill residue layer
24
formed simultaneously over the small areas
13
and large areas
14
on the surface of the first layer
15
when the blanket conformal fill layer
20
is planarized through the CMP planarization method to form the planarized filled recesses
21
and
22
. As is understood by a person skilled in the art, when planarizing large areas of the blanket conformal fill layer
20
, generally of dimensions greater than about 1000 microns, the blanket conformal fill layer
20
will in addition to planarizing more rapidly over the wide recess
12
and forming a dish within the planarized filled recess
22
simultaneously also polish more slowly over the large area
14
on the surface of the first layer
15
and leave the fill residue layer
24
formed over the large area
14
on the first layer
15
. Attempts to remove the fill residue layer
24
by further planarization will cause increased dishing of the planarized filled recesses
21
and
22
. Fill residue layers such as the fill residue layer
24
are undesirable since they impede further device processing on the planarized surface.
A method to limit dishing is used in U.S. Pat. No. 5,721,172, issued Feb. 24, 1998, to Jang et al., entitled, “Self-Aligned Polish Stop Layer Hard Masking Method For Forming Planarized Aperture Fill Layers”. A conformal polish stop layer is formed on top of the conformal fill layer. The conformal polish stop layer and the conformal aperture fill layer are then planarized through a first CMP planarization method until there is reached the lower planar region of the conformal polish stop layer, while simultaneously forming a patterned polish stop layer and a partially CMP planarized aperture fill layer. The patterned polish stop layer is then employed as a etch mask to form an etched partially CMP planarized aperture fill layer with a protrusion over the aperture, where the height of the protrusion compensates for a dish which would otherwise form when the etched partially CMP planarized aperture fill layer is planarized through a second CMP method to form a planarized aperture fill layer within the aperture. The teaching of this document requires a complicated process involving the deposition of an extra layer and two separate CMP planarization steps. The method of CMP in this teaching also requires relatively low selectivity between the fill layer and the polish etch stop layer. Therefore the polish etch stop layer final thickness is not well controlled.
An Article by B. H. Roh et al. entitled “Easily Manufacturable Shallow Trench Isolation for Gigabit Dynamic Random Access Memory”, Jpn. J. Appl. Phys. Pt. 1,Vol.35 (1996), pp.1618-4623 describes a method to limit the dishing phenomenon in shallow trench isolation techniques. The oxide isolation layer is partially etched on a semiconductor active region prior to performing a planarization step. The result of this method is a planarized oxide surface. There is no n
Brazas, Jr. John C.
Jech, Jr. Joseph
Lebens John A.
Close Thomas H.
Eastman Kodak Company
Mulpuri Savitri
Shaw Stephen H.
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