Dynamic burn-in test equipment

Details Dynamic burn-in test equipment Dynamic burn-in test equipment

2000-01-05

2001-04-10

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C324S1540PB, C714S724000

Reexamination Certificate

active

06215324

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei 11-2080 filed in Jan. 7, 1999 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reliability test equipment and a failure rate test equipment. More particularly, the present invention relates to a dynamic burn-in test equipment for testing large scale integration chips (LSI chips) sealed in packages each having a large number of I/O pins. Here, the LSI chips may include very large scale integration chips (VLSI chips), ultra large scale integration chips (ULSI chips) or gigascale integration chips (GSI chips).
2. Description of the Related Art
In recent years, the operation speeds, the memory capacities, and the numbers of bits of semiconductor devices are considerably increasing. As high-speed semiconductor devices, devices having operation frequency higher than 500 MHz, e.g., reduced instruction set computer (RISC) like microprocessor units (MPUs) have been developed. The number of pins of a package is also rapidly increasing. In this manner, the development of the semiconductor devices advances, new functions are successively added to the semiconductor devices. Accordingly, a testing technique such as a reliability test must keep in step with the development of devices. However, the development speed of semiconductor devices acceleratively increases, miscellaneous new functions to be added to the semiconductor devices become varied. Nowadays, the development speed of the testing technique is gradually behind the development speed of the semiconductor device. In particular, it has been very difficult to perform a reliability test for multi-pin LSI chips within a short test time and at a low cost.
In order to calculate failure rates of LSI chips as correct as possible, a large number of products must be tested for a very long test period. If the values of failure rates calculated as results of the test are equal to each other, the statistical “validities” of the failure rates are considerably different from each other depending on the numbers of tested products.
In general, the failure rate versus age (or “time in use”) curve follows the well-known shape of the of the “bathtub curve” shown in FIG.
1
. The failures are typically grouped into one of three categories: infant mortality, useful life, and wearout failures. The infant mortality failures, also called “early failures” or “patent failures” occur during early product life cycle, and by definition, the failure rate decreases with age. After the infant mortality failures are culled out, the component settle into a long period of useful life failure, called “over stress failures” or “intrinsic failures” which are caused by high-level stress outside those expected in normal usage. Finally, wearout failures begin to be significant as normal wear out mechanisms start to take their toll on components that are manufactured within acceptable specifications. Since the wearout failures occur considerably later than rated lifetime of semiconductor devices in general, the failure rate versus age curves in the infant mortality and the useful life stages are important. Therefore, in order to obtain meaningful qualification test data, the bathtub curve shown in
FIG. 1
must be plotted so as to identify one of three failure mechanisms, by focusing on the failure rate versus age curve, calculated by the result of the test.
In general, “burn-in testing”, or component testing where infant mortality failures are screened out by testing at elevated voltages and temperatures for a specified length of time, serving as an accelerated environment testing, is performed to plot in a short test period the failure rate versus age curves as shown in FIG.
1
. On the assumption that the chemical reaction rate associated with the failure mechanism is expressed by an exponential function and has a positive temperature coefficient according to Arrhenius' equation, the test temperature is elevated to make the device failure conspicuous. Acceleration coefficient B of a failure rate is generally given by:
B
=exp{−(&Dgr;
E/k
)·(1
/T
jH
1
/T
jF
)}  (1)
where &Dgr;E: activation energy of a failure [eV], k: Bolzmann's constant=8.617×10
−5
[eV/K], T
jH
: p-n junction temperature [K] of an LSI chip at the elevated temperature in the accelerated environment testing, and T
jF
: p-n junction temperature [K] of the LSI chip under normal and actual usage condition.
A perfect product must have an endless lifetime. More specifically, a limited lifetime is caused by the presence of any defect. If the defect is accelerated and increased by the elevated temperature under the test condition, the product is recognized as a defective. We can understand that the burn-in testing is conducted on the assumption that the long lifetimes of products that are able to pass the accelerated environment testing can be secured.
Since it is desirable to complete a reliability evaluation testing in a short test time, the reliability evaluation testing should be performed at an elevated temperature which is as high as possible. However, an annealing temperature is limited to a predetermined value because good products must not be damaged. According to such a consideration, the burn-in testing is performed at a limited elevated temperature at which the validity of acceleration can be recognized.
The characteristic feature of the burn-in testing is that the semiconductor device is tested at the elevated temperature, while supplying predetermined supply voltages. As a typical failure mechanism of LSI chips, an imperfect metallization or connection is known. Since the resistance of the interconnection is desired to be low, unexpected heat is generated at the interconnection where the resistance of the interconnection is high due to, for example, flaw, void, electromigration, corrosion, or non-ohmic contact. This means that a large acceleration coefficient is applied to only the weak portion.
When signals are given to an LSI, or a device under test (DUT) at random, all the internal circuits of the DUT cannot be operated. Therefore, a predetermined test pattern adjusted for an LSI test equipment is used for a reliability evaluation testing of the LSI chip. More specifically, in the burn-in testing, a test pattern generator (signal generator) having the same function as that of the LSI test equipment is required. Since the internal circuits of the LSI chip are operated by miscellaneous signals generated by the signal generator, such a test method for the LSI chip is called “dynamic burn-in testing”. On the other hand, a burn-in testing in which any signal in the internal circuits of the LSI chip does not change at all under a high-temperature accelerated environment, while power supply lines are only connected to the LSI chip, is called “static burn-in testing”. And, in this connection, a high-temperature accelerated environment testing in which even the power supply lines are not connected to the LSI chip is called a “high-temperature shelf life testing”. Of the three test methodologies, the static burn-in testing and the high-temperature shelf life testing are mainly used at present. The static burn-in testing generally requires 8 to 16 hours. However, since the dynamic burn-in testing can drive all the internal circuits in the LSI chip, a local temperature in the LSI chip increases, and the dynamic burn-in testing is expected to be able to perform a testing in a shorter test period than that of the static burn-in testing. However, in a conventional static burn-in technique, the static burn-in testing requires very long test time. That is, the conventional static burn-in technique can be performed only when the numbers of pins of LSI chip serving as DUT are very small, and the numbe

Affiliated with

Also associated with

Rating

Dynamic burn-in test equipment does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic burn-in test equipment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic burn-in test equipment will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2484094