Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-09-02
2001-09-11
Hsu, Alpus H. (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S397000
Reexamination Certificate
active
06289014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cell header conversion apparatus and the method of handling a plurality of communication lines (hereinafter called a “multiline”) for converting route information set in the header of a packet such as a cell, etc., and a computer-readable storage medium storing a program which enables a computer to perform processing to implement the method.
2. Description of the Related Art
In an ATM (Asynchronous Transfer Mode) network, information is transmitted in units of cells with a fixed length of 53 bytes in total (a kind of length-fixed packet) from a transmitting terminal to a receiving terminal, by being split into 48 bytes and being provided with a header of 5 bytes as address label information. A cell transmitted to an ATM network is switched at a high speed at each node by way of hardware according to a VPI (Virtual Path Identifier) and a VCI (Virtual Channel Identifier) in the header. For a form of switch unit provided in each of the nodes a self-routing switch is widely known, in which the cell selects its own communication route according to the header, in the switch unit using a routing tag attached to the cell. When the cell is received by a target receiving terminal, the header of the cell is verified at the receiving terminal, and the cell is restored to the original information. Here, a VPI is an identifier which is used to identify a VP (Virtual Path) being a plurality of virtual communication paths established between each node in a network, and a VCI is an identifier used to identify a VC (Virtual Channel) being a virtual communication channel in the VP.
Since when an ATM connection is established, peculiar VPI and VCI are assigned to each link between nodes, the values of the VPI and VCI are converted every time the cell passes through each node. This conversion is performed by a header rewrite unit in the node rewriting the VPI and VCI in the cell. For this header conversion process method a conversion method using a simple table or a conversion method by a matching process using a CAM (Contents Association Memory) is generally adopted.
Recently the need for a multiline has increased due to improvements in the integration of LSIs. The multiline has a merit of being capable of reducing costs per subscriber by replacing one subscriber interface/1PWCB (Printed Wiring Circuit Board) with a plurality of subscriber interfaces/1PWCB. In order to implement a multiline,for example, it is necessary to attach to the header of a cell a line identifier (hereinafter called “TAGD”)for newly indicating the line order of the multiline in the network node of an ATM switching equipment,etc.
Namely, in order to increase the number of network interfaces of a node, it is necessary to attach appropriate VPI, VCI and TAGD to the cell transferred within the network according to the VP, VC and line in a target route at each node, and thereby the cell is transferred to its final destination.
FIG. 1
explains a TAGD-attached cell header conversion method using a simple table as a first prior art, and shows a configuration in the case where the VPI, VCI and TAGD of an input cell
11
are converted into the VPI, VCI and TAGD of an output cell
12
.
FIG. 2
explains the boundary control process in the boundary control unit
13
shown in FIG.
1
.
FIG. 3
shows data stored in the conversion table
14
shown in
FIG. 1
as entries.
As shown in
FIG. 1
, in the case of an NNI (Network Node Interface), the VPI, VCI and TAGD in the header of the input cell
11
are 12 bits (8 bits in the case of a UNI (User Network Interface), for the case of an NNI and UNI, described later), 16 bits and 9 bits, respectively, and the input cell
11
is inputted to the boundary control unit
13
. In the boundary control unit
13
a predetermined number of bits on the LSB (Least Significant Bit) side of VPI, VCI and TAGD are extracted from the total of 37 bits (33 bits in the case of UNI) consisting of VPI, VCI and TAGD as actually used effective bits, and the entry address of the conversion table
14
is generated by combining these effective bits. In the example shown in
FIG. 2
, the boundary control unit
13
extracts a bits of VPI
16
a, b
bits of VCI
16
b
and
c
bits of TAGD
16
c
from the header of the input cell
11
, generates (a+b+c) bits of an address
17
by combining them, and performs a boundary control process for outputting this address
17
as the entry address of the conversion table
14
. 37 bits in total of data
18
consisting of the post-conversion VPI (12 bits), post-conversion VCI (16 bits) and post-conversion TAGD (9 bits) in the conversion table
14
shown in
FIG. 3
which are stored in the address outputted from the boundary control unit
13
are outputted to a header rewrite unit
15
. The header rewrite unit
15
rewrites the VPI (12 bits), VCI (16 bits) and TAGD (9 bits) of the header of the input cell
11
to the post-conversion VPI (12 bits), post-conversion VCI (16 bits) and post-conversion TAGD (9 bits) inputted from the conversion table
14
, and outputs the cell with the rewritten header as an output cell
12
.
FIG. 4
shows a matching process using a CAM as a second prior art, explains a TAGD-attached cell header conversion method, and shows a configuration in the case where the VPI, VCI and TAGD of the input cell
21
are converted to the VPI, VCI and TAGD of the output cell
22
.
FIG. 5
shows data stored in the entry of a matching table
25
.
As shown in
FIG. 4
, a matching detector unit
24
controls an address counter
26
, compares the total of 37 bits of data consisting of the VPI, VCI and TAGD of the input cell
21
with the total of 37 bits of data
27
a consisting of pre-conversion VPI, pre-conversion VCI and pre-conversion TAGD being a part of data
27
stored in each entry of the matching table
25
shown in
FIG. 5
, and reads the total of 37 bits of data
27
b consisting of the post-conversion VPI, post-conversion VCI and post-conversion TAGD shown in
FIG. 5
of the entry in which the pre-conversion VPI, pre-conversion VCI and pre-conversion TAGD matching with the VPI, VCI and TAGD of the input cell
11
are stored, from the matching table
25
as the VPI, VCI and TAGD of the output cell
22
. Then, the matching detector unit
24
outputs the total of 37 bits of the data
27
a consisting of the VPI, VCI and TAGD of the output cell
22
to a header rewrite unit
23
. The header rewrite unit
23
rewrites the total of 37 bits consisting of VPI, VCI and TAGD set in the header of the input cell
21
to the total of 37 bits consisting of VPI, VCI and TAGD (the data
27
b) inputted from the matching detector unit
24
to generate an output cell
22
.
A UNI is an interface between a user's terminal and a network, and an NNI is an interface between two network nodes (for example, two items of ATM switching equipment).
The header conversion method using a simple table as the first prior art has a drawback in that as the total effective bit length of the VPI, VCI and TAGD becomes large, the memory capacity of the conversion table
14
also becomes large. For example, when the total bit length of the VPI, VCI and TAGD of the header of the input cell
11
is 37 bits, if the effective bit length of a VPI a for performing a boundary control using the boundary control unit
13
, the effective bit length of a VCI b, and the effective bit length of a TAGD c, are assumed to be 6 bits, 10 bits and 2 bits, respectively, the number of addresses (number of entries) of the conversion table
14
is at the most 2
18
bits, and the capacity of a RAM needed when the conversion table
14
is composed of a RAM is approximately 2
18
×37=9.7 Mbits. However, the RAM capacity needed when a=12, b=16 and c=5 becomes 2
33
×37=317.82 Gbits. In an actual operation the processing of the number of bits nearly equal to the latter is required. Accordingly, when the total effective bit length of the VPI, VCI and TAGD is large, this method requires a me
Aihara Naoki
Hayami Hichiro
Hoshino Tadashi
Fujitsu Limited
Helfgott & Karas P.C.
Ho Duc
Hsu Alpus H.
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