Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-09-01
2001-04-10
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000, C345S068000
Reexamination Certificate
active
06215463
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a driving system of a matrix display system used as a display for an information terminal device, personal computer, and television receiver, and having such a display panel as an alternative current plasma display panel (ACPDP), electroluminescence (EL) panel, and liquid crystal panel wherein capacitive load is generated, and more particularly to a system wherein power for applying pixel data pulses to capacitive column electrodes is effectively reduced.
Recently, as a display device becomes large in size, thickness of the display device is desired to be thin. Therefore, various types of display devices of thin thickness are provided. As one of the display devices, an ACPDP is known.
A conventional ACPDP comprises a plurality of column electrodes and a plurality of row electrodes formed in pairs and disposed to intersect the column electrodes. A pair of row electrodes form one row (one scanning line) of an image. The column electrodes and the row electrodes are covered by dielectric layers respectively, at a discharge space. At the intersection of each of the column electrodes and each pair of row electrodes, a discharge cell (pixel) is formed.
FIG. 4
shows a timing chart of drive signals for driving the conventional ACPDP.
A reset pulse RPx of negative polarity is applied to each of the row electrodes X
1
-Xn. At the same time, a reset pulse RPy of positive polarity is applied to each of the row electrodes Y
1
-Yn. Thus, all of the row electrodes in pairs in the PDP are excited so that discharge occurs in each discharge cell, thereby producing charged particles in the discharge cell. Thereafter, when the discharge is finished, wall charge is formed and accumulated on the discharge cell (A reset all at once period).
Then, pixel data pulses AP
1
-APn corresponding to the pixel data for every row are applied to the column electrodes A
1
-Am in order in accordance with display data. At that time, scanning pulses (selecting and erasing pulses) SP are applied to the row electrodes Y
1
-Yn in order in synchronism with the timings of the data pulse AP
1
-APn.
At the time, only in the discharge cell (non-lighting pixel) to which the scanning pulse SP and the pixel data pulse AP are simultaneously applied, the discharge occurs, so that the wall charge produced at the reset all at once period is erased.
On the other hand, in the discharge cell to which only the scanning pulse SP is applied, the discharge does not occur. Thus, the wall charge produced at the reset all at once period is held. Namely, a predetermined amount of the wall charge is selectively erased in accordance with the pixel data (An address period).
Next, a discharge sustaining pulse IPx of negative polarity is applied to the row electrodes X
1
-Xn, and a discharge sustaining pulse IPy of negative polarity is applied to the row electrodes Y
1
-Yn at offset timing from the discharge row pulses IPx.
During the discharge sustaining pulses are continuously applied, the discharge cell which holds the a wall charge sustains the discharge and emission of light (A discharge sustaining period). On the other hand, a discharge cell in which the wall charge is erased does not emit.
Then, wall charge erasing pulses EP are applied to the row electrodes Y
1
-Yn for erasing the wall charges formed in all discharge cells.
By repeating the cycle comprising the reset all at once period, address period, discharge sustaining period, and wall charge erasing period, the pixel display is performed.
In such a driving system, there may be generated a potential difference between a column electrode to which a pixel data pulse is applied and an adjacent column electrode to which no pixel data pulse is applied during the address period. Therefore, a parasitic capacity between the adjacent column electrodes must be charged and discharged every time the pixel data is written on the scanning line. As a result, reactive power generates. In the case where only a single color, namely, red, green or blue is shown on the display, the reactive power is increased so that a large power for writing pixel data is required in addition to the power necessary for displaying. Hence the power consumption is increased.
In order to decrease the parasitic capacitance, which causes the increase in power consumption as described above, it is necessary to increase the distance between column electrodes, which renders it difficult to produce a extremely fine display panel.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a driving system for a display panel wherein the power consumption is reduced and the fine the display panel is still achieved.
According to the present invention, there is provided a driving system for a display panel having a plurality of row electrodes, a plurality of column electrodes intersecting with the row electrodes, comprising, a data voltage source circuit having a voltage source for supplying a voltage of about one half of a maximum voltage for driving the column electrode, a diode provided between the voltage source and an output terminal, a first switch connected to the voltage source at an end thereof, a second switch connected to another end of the first switch at an end thereof, and to a ground at the other end, and a voltage adding capacitor provided between a junction of the first and second switches and the output terminal, a column driver for driving the column electrodes, the column driver having an input terminal connected to the output terminal of the data voltage source circuit, a plurality of output terminals connected to the column electrodes, a third switch provided between the input terminal and each of the output terminals, a fourth switch provided between each of the output terminals and a ground, control circuit means for producing control signals for controlling the first to fourth switches.
These and other objects and features of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.
REFERENCES:
patent: 5717437 (1998-02-01), Sano et al.
Ide Shigeo
Matsumoto Yukihiro
Arent Fox Kintner & Plotkin & Kahn, PLLC
Dinh Duc
Hjerpe Richard
Pioneer Electronic Corporation
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