Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1999-04-05
2001-06-19
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S200000, C365S189090, C365S226000, C365S063000
Reexamination Certificate
active
06249475
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more specifically to integrated circuit memories.
BACKGROUND OF THE INVENTION
With each new generation of semiconductor memory, the size and density of the memory array increases. For example, when moving from a 4Mb technology to a 16Mb design, the array area must be increased in order to accommodate the additional memory cells. Increasing the array size, however, adversely effects certain electrical parameters required for optimal circuit performance.
In particular, increasing the size of the memory array leads to a problem known as “resistance droop”. In the memory array, long interconnect wires are used to carry voltages across the memory array. When a voltage source is connected to a long interconnect wire, a voltage drop is created on the interconnect wire due to the resistance of the interconnect wire. More specifically, points on the interconnect wire which are located far from the voltage source have a lower voltage potential than those which are located near the voltage source. This voltage differential in the memory array can adversely effect circuit performance and circuit yield.
Accordingly, a need exists for an efficient way to design and fabricate integrated circuits having memory arrays with reduced “resistance droop.”
SUMMARY OF THE INVENTION
The present invention overcomes the problems of the prior art memory circuits by providing a method for designing a tiled memory with distributed charge source supply. In accordance with the present invention, each of the memory tiles in the tiled memory array is designed to have charge source circuitry which provides sufficient reference voltages for proper operation of the memory tile. In addition, each memory tile may be designed to include local error detection and correction circuitry. To facilitate reliable operation, each memory tile may also be designed to include redundant rows and/or columns, and appropriate redundancy control circuitry. According to one embodiment of the present invention, an integrated circuit device may be designed having a plurality of the memory tiles arranged to form a tiled memory array.
In one aspect of the present invention, the method includes the steps of designing a memory cell, arranging a plurality of said memory cells in a cell array, determining the charge requirements of said cell array, designing a charge source to supply said charge requirements, and integrating said charge source and said cell array to form said memory tile.
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Atwell William Daune
Longwell Michael L.
Myers Jeffrey Van
Auduong Gene N.
Cooper Kent J.
Godsey Sandra L.
Madrone Solutions, Inc.
Myers Jeffrey Van
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