Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1999-03-24
2001-08-28
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S784000
Reexamination Certificate
active
06281580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an LSI package and an inner lead wiring method for same, and more particularly to a face up ball grid array (BGA) package and an inner lead wiring method for same.
2. Description of the Related Art
In recent years, as demand for smaller, cheaper LSI packages for use in electronic equipment has increased, the BGA package has come to replace the quad flat package (QFP) as the LSI package of choice due to its smaller surface area and greater ease of installation.
The face up BGA package in particular comprises a chip having a plurality of bonding pads and a package substrate for mounting the chip. A plurality of terminals are arranged on a grid on a surface of the package substrate on which the chip is mounted, and a plurality of lead pads are aligned around the periphery of the package substrate.
The plurality of bonding pads on the chip are connected by bonding wire to the corresponding respective lead pads on the package substrate and the plurality of lead pads are connected by inner leads to the corresponding respective terminals.
It should be noted that there is a limit to the length of the bonding wire. If the bonding wire is too long, then the resistance and inductance of the bonding wire increase to the point that the characteristics of the chip may be lost. In addition, assembly and production output may decline.
Accordingly, as the size of the chip mounted on the package substrate decreases the limitation on the length of the bonding wire results in the lead pads aligned around the periphery of the package substrate being positioned closer to the center of the package substrate.
However, as described above, with the face up BGA package the position of the lead pad changes according to the size of the chip mounted on the package substrate. As a result, it is very difficult to configure the package so that the same lead pad and terminal are securely connected without crossed wiring regardless of changes in the size of the chip, that is, so that so-called pin compatibility is maintained. Therefore a low-cost face up BGA package that maintains pin compatibility regardless of changes in the size of the chip is desirable.
With the conventional face up BGA package, attempts have been made to maintain pin compatibility by, for example, changing the position of the bonding pads provided on the chip or by using multilayer wiring of the inner leads connecting the lead pads and the terminals.
However, changing the position of the bonding pads according to the size of the chip requires altering the layout of the chip itself, which is time-consuming and costly.
Moreover, there is the additional problem that other types of package variations, for example pin grid array (PGA) QFP, are rendered unusable with the chip even when available, because the chip layout has been altered by the changing of the position of the bonding pads.
Additionally, multilayering of the inner lead wiring raises the cost of the package, offsetting the lower-cost advantage of the reduction in chip size that was one of the original reasons for adopting the BGA package in the first place.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an LSI package and an inner lead wiring method for same, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a face up BGA package that can be produced quickly and at low cost, and that maintains pin compatibility without the need to alter the position of the bonding pads even when changing the size of the chip, and an inner lead wiring method for same.
In particular, the above-described objects of the present invention are achieved by an LSI package comprising:
a chip; and
a package substrate on which are provided a plurality of terminals and a plurality of lead pads, the lead pads connected by bonding wire to the chip,
wherein the plurality of lead pads and the plurality of terminals are connected by inner leads provided on an upper surface of the package substrate, the plurality of terminals including nonconnection terminals not connected to corresponding inner leads for which external electrical connection of the chip is unnecessary, the nonconnection terminals positioned at predetermined positions regardless of the position of the lead pads provided on the upper surface of the package substrate.
By providing the LSI package as described above, it is possible to prevent the occurrence of short circuits between inner leads as well as a shortage of wiring space. As a result, it is possible to always connect in identical combinations each of the remaining leads with their corresponding lead pads on a one-to-one basis, regardless of the actual position of the lead pads on the package substrate. That is, even though the position of the lead pads on the package substrate changes as the size of the chip mounted on the package substrate decreases, there is no change in the corresponding relation between the LSI package terminals and the chip terminals, that is, the bonding pads, connected to the lead pads by bonding wire. As a result, LSI package pin compatibility is maintained.
Additionally, it should be noted that it is possible to provide these nonconnection terminals in a quantity equal to the difference between the number of terminals on the package substrate and the number of terminals, that is, bonding pads, on the chip.
Additionally, the above-described objects of the present invention are also achieved by the LSI package as described above, wherein at least some of the plurality of terminals are connected by the inner leads to corresponding lead pads via the nonconnection terminals.
By providing the LSI package described above, it is possible to connect terminals for which inner lead wiring space on the package substrate has disappeared because the size of the chip mounted on the package substrate has decreased to their corresponding lead pads via the nonconnection terminals. As a result, it is possible to maintain the same corresponding relation between the LSI package terminals and the chip terminals, that is, the bonding pads, connected to the lead pads by bonding wire as existed before the size of the chip was decreased, thereby maintaining LSI package pin compatibility.
Further, the above-described objects of the present invention are also achieved by the LSI package as described above, wherein the LSI package comprises a face up BGA package.
By providing an LSI package comprising a face up BGA package, it is possible to provide a face up BGA package that maintains pin compatibility.
Additionally, the above-described objects of the present invention are also achieved by an inner lead wiring method for the LSI package as described above, the inner lead wiring method comprising the steps of:
(a) selecting the nonconnection terminals not connected to corresponding inner pads for which external electrical connection of the chip is unnecessary, positioned at predetermined positions regardless of the position of the lead pads positioned on the upper surface of the package substrate; and
(b) wiring the inner leads so as to connect terminals other than the nonconnection terminals and corresponding lead pads.
By providing the inner lead wiring method described above, it is possible to select the terminals that will be nonconnection terminals and to always connect in identical combinations each of the remaining terminals with their corresponding lead pads on a one-to-one basis, thereby maintaining LSI package pin compatibility.
Further, the above-described objects of the present invention are also achieved by the inner lead wiring method as described above, the method further comprising the step of connecting terminals having no space in which to connectably wire the inner leads and corresponding lead pads via the nonconnection terminals by using the inner leads.
By utilizing the nonconnection terminals to connect to their corresponding lead pads those terminals fo
Ise Hisao
Takahashi Hitoshi
Armstrong Westerman Hattori McLeland & Naughton LLP
Cao Phat X.
Chaudhuri Olik
Fujitsu Limited
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