Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-10-13
2001-09-04
Berhane, Adolf Deneke (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06285174
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to switching controllers for use in switching DC-to-DC converters, in which the duty cycle of each power channel is controlled by a pulse width modulated control signal. More specifically, the invention is a method and circuit for generating a train of pulses whose width is indicative of the nominal power switch on-time needed to produce a DC output potential V
out
in response to a DC input potential V
in
. The pulse train is useful in a switching controller for a DC-to-DC converter.
2. Description of the Related Art
For convenience, we will use the expression “switching controller” chip below to denote either a controller (implemented as an integrated circuit) which generates power switch control signals for at least one power switch implemented external to the chip (typically multiple power switches, each implemented external to the chip), or a switching “regulator” (implemented as an integrated circuit) which generates such power switch control signals and which also includes at least one power switch implemented on-board the chip (typically multiple power switches, each implemented on-board the chip ). The power switches are typically MOSFET devices.
One type of conventional switching power supply which employs current mode control to achieve output voltage regulation is a DC-to-DC converter including a current mode switching controller chip, and circuitry external to the controller chip which defines one or more power channels (e.g., multiple paralleled power channels). Each power channel includes an inductor and at least one power switch. The controller chip includes a control signal channel for each power channel. Each control signal channel generates a pulse width modulated power switch control signal in response to a feedback signal (a ramped voltage) indicative of the current through the channel's inductor, and a second feedback signal indicative of the DC-to-DC converter's output potential. This allows control of the time-averaged duty cycle of each of the channel's power switches. Typically, a ramped voltage (internally generated in the controller chip) adjusts the effective ramp rate slightly for improved stability through a technique called “slope compensation.” The adjusted feedback signal (e.g., one whose value is the difference between the second feedback signal and the internally generated ramped voltage) controls the peak value to which the inductor is allowed to ramp up. Also typically, each pulse width modulated power switch control signal is a binary signal having periodically occurring leading edges, and trailing edges which occur at times determined by the instantaneous value of the feedback signal.
Some DC-to-DC converters include a current mode switching controller chip and buck converter circuitry external to the controller chip. The buck converter circuitry comprises an NMOS transistor (which functions as a power switch, and has a drain coupled to the DC-to-DC converter's input node), an inductor and a current sense resistor (connected in series with the channel of the NMOS transistor), a Schottky diode (coupled between ground and the source of the NMOS transistor), an output capacitor coupled between ground and the output node, and a feedback resistor divider coupled between ground and the output node.
In order to generate a pulse width modulated power switch control signal in response to feedback (or in response to a DC signal which corresponds to a desired DC-to-DC converter output potential V
out
), it would be desirable for DC-to-DC converter switching controller chips (of many different types) to include circuitry for generating a train of pulses whose width is indicative of the nominal power switch on-time needed to produce a DC output potential V
out
in response to a DC input potential V
in
. It would be especially useful for the circuitry to do so in an accurate manner, independently of process variations (i.e., variations in the manufactured characteristics of integrated circuits produced using the same design) and variations in operating temperature.
SUMMARY OF THE INVENTION
In a class of embodiments, the invention is an on-time signal generation circuit for use in a switching DC-to-DC converter. The on-time generation signal circuit includes a comparator, a ramp generator (whose output is coupled to one input of the comparator), and an amplifier (whose output is coupled to the other input of the comparator). The ramp generator is configured to generate a periodic ramped potential having peak level kV
in
and period T
osc
, where Vin is the input potential of a DC-to-DC converter and T
OSC
is the DC-to-DC converter's switching period. Preferably, the ramp generator includes a transconductance amplifier having an input coupled to receive the input potential V
in
of the DC-to-DC converter and configured to assert a current I
2
(where I
2
=gm
2
(V
in
)=V
in
/R
2
), ramp generation circuitry (including a capacitor and a switch coupled to periodically discharge the capacitor), and an oscillator coupled and configured to assert control signals to the switch for periodically discharging the switch with period T
OSC.
The amplifier has an input coupled to receive a DC potential V
out
, where V
out
is the DC-to-DC converter's output potential or a DC signal which corresponds to a desired level for the DC-to-DC converter's output potential (i.e., a DC potential which is proportional to a desired level for the DC-to-DC converter's output potential with a proportionality constant that can but need not equal one), and is configured to assert an amplified potential kV
out
in response thereto, where k is the same coefficient as in the peak level kV
in
of the ramped voltage produced by the ramp generator. In response to potential kV
out
from the amplifier and the ramped voltage kV
in
, from the ramp generator, the comparator asserts a binary pulse train comprising pulses T
ON
. The leading edges of pulses T
ON
occur with period T
OSC
. The trailing edge of each pulse T
ON
occurs when ramped voltage kV
in
rises to a level matching kV
out
. Thus, the width of each pulse T
ON
is equal to T
OSC
(V
out
/V
in
), and the width of each pulse T
ON
is indicative of the nominal (or critical) power switch on-time needed for the DC-to-DC converter (in the case that it is a step down DC-to-DC converter) to produce output potential V
out
(during steady-state operation) in response to input potential V
in
.
Preferably, the on-time signal generation circuit is implemented so that the width of each pulse T
ON
is accurately equal to T
OSC
(V
out
/V
in
), independently of process variations and variations in operating temperature. Preferably, the width of each pulse T
ON
is caused to be equal to T
OSC
(V
out
/V
in
), independently of operating temperature, by implementing the ramp generator and amplifier so that the factor “k” in the peak level kV
in
, of the ramped voltage (produced by the ramp generator) is equal to k=(C
1
/C
2
)(R
3
/R
2
), where C
1
and C
2
are the capacitances of periodically discharged capacitors in the ramp generator and R
3
and R
2
are resistances of resistive elements in the ramp generator.
Preferably also, the ramp generator of the on-time signal generation circuit includes circuitry for compensating for the delay time of the comparator. In a preferred implementation, the ramp generator includes a transconductance amplifier configured to assert a current I
2
=gm
2
(V
in
)=V
in
/R
2
, ramp generation circuitry (including a current multiplying circuit having an input which receives current I
2
and an output (coupled to a first input of the comparator) which asserts a current I
4
which is proportional to
12
, a capacitor which is charged by the output current of the current multiplying circuit, and a switch coupled to periodically discharge the capacitor with period T
OSC
), an oscillator coupled and configured to assert control signals for periodically discharging the s
Berhane Adolf Deneke
Girard & Equitz LLP
National Semiconductor Corporation
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