Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – In integrated structure
Reexamination Certificate
1999-02-08
2001-07-31
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
In integrated structure
C257S471000, C257S484000, C257S369000, C257S401000, C257S382000, C257S384000
Reexamination Certificate
active
06268636
ABSTRACT:
TECHNICAL AREA
The present invention relates to semiconductor devices, and more particularly comprises semiconductor devices which include junctions that rectify when the semiconductor is doped either N or P-type, by either metalurgical or field induced means. A preferred embodiment is formed in intrinsic semiconductor and is a simple to fabricate single device which operates similarly to conventional dual device CMOS, under described biasing schemes.
BACKGROUND
MOSFETS, CMOS, gate voltage controlled direction of rectification, and single device inverting and single device non-inverting MOS semiconductor devices which demonstrate operating characteristics similar to those of multiple device Complimentary Metal Oxide Semiconductor (CMOS) systems have been previously described in U.S. Pat. No. 5,663,584 to Welch, and said 584 patent is incorporated hereinto by reference. Semiconductor devices described in said 584 patent operate on the basis that materials exist which produce a rectifying junction with semiconductor channel regions when they are doped either N or P-type, whether said doping is achieved via metalurgical or field induced means. Said materials typically form junctions that are termed “Schottky barrier” junctions with semiconductors, (in contrast to P-N Junction), however, said terminology is not to be considered limiting to the present invention based upon technical definitions of the terminology “Schottky barrier”, and where the terminology “Schottky barrier” junction is utilized in this Disclosure it is to be understood that it is used primarily to distinguish a junction described thereby from “P-N” junctions, and to identify junctions between a semiconductor and an element which are rectifying whether N or P-type Doping is present in the semiconductor, and whether said doping is present as the result of metalurgical or field induced means.
Another patent, U.S. Pat. No. 5,760,449 to Welch describes Source Coupled Regeneratively Switching CMOS formed from a seriesed combination of N and P-Channel MOSFTES which each demonstrate the special operating characteristics of conducting significant current flow only when the Drain and Gate of a 449 patent MOSFET are of opposite polarity, and the Gate polarity is appropriate to invert a channel region. Said 449 patent is incorporated hereinto by reference, as are co-pending application Ser. Nos. 09/033,695 and 60/081,705 and 60/090,565. Also disclosed are patents to Lepselter, U.S. Pat. No. 4,300,152; Koeneke et al., U.S. Pat. No. 4,485,550; Welch, U.S. Pat. No. 4,696,093; Mihara et al., U.S. Pat. No. 5,049,953 and Homna et al. U.S. Pat. No. 5,177,568. A relevant article titled “SB-IGFET: An Insulated Gate Field Effect Transistor using Schottky Barrier Contacts for Source and Drain”, by Lepselter & Sze, Proc. IEEE, 56, January 1968, pp. 1400-1402, is also identified in said 584 patent. Further, a a paper by Lebedov & Sultanov, titled “Some Properties of Chromin-Doped Silicon”, Soviet Physics, Vol. 4, No. 11, May 1971 is identified as it discusses formation of a rectifying junction by diffusion of chromium into P-type Silicon. A paper by Hogeboom & Cobbold, titled “Etched Schottky Barrier MOSFETS Using A Single Mask, Electronics Letters, Vol. 7, No. 5/6, (March 1971) is also included as it describes formation of Schottky barrier MOSFETS by deposition of Aluminum onto semiconductor. Also mentioned, and included herein by reference for general insight to semiconductor circuits and systems, is a book titled “Microelectronic Circuits” by Sedra and Smith, Saunders College Publishing, 1991. Likewise mentioned, and included herein by reference for the purpose of providing insight into semiconductor device fabrication, is a book titled “Physics and Technology of Semiconductor Devices”, by Grove, John Wiley & Sons, 1967; and a book titled “Electronic Materials Science: For Integrated Circuits in Si and GaAs”, Mayer & Lau, MacMillan, 1990.
Even in view of the cited Welch U.S. Pat. Nos. 5,663,584 and 5,760,449 patents, and co-pending CIP applications derived therefrom which describe inverting and non-inverting single device equivalents to conventional CMOS, regeneratively switching N and P-Channel source coupled CMOS, and the blocking of parasitic current flows in semiconductor systems by use of material which forms rectifying junctions with either N or P-type semiconductor whether said doping is metallurgically or field induced; there remains need for clarification and description of biasing and switching operational characteristics of single device equivalents to CMOS, particularly where essentially intrinsic, or lightly doped, semiconductor is beneficially utilized as device isolating semiconductor substrate material.
DISCLOSURE OF THE INVENTION
The present invention is primarily a semiconductor device in a semiconductor substrate, comprising at least one junction which is formed by introduction of non-semiconductor substrate material(s) to said semiconductor substrate, wherein said non-semiconductor substrate material(s) form a rectifying junction with either N and P-type semiconductor, whether said doping is metallurgically or field induced. Said non-semiconductor components can be material(s) or dopants entered to a semiconductor substrate by, for instance, a procedure comprising vacuum deposition, ion-implantation and/or pre-deposition and diffusion, each where appropriate accompanied by annealing. And, it is noted that the semiconductor substrate can, prior to the fabrication of present invention semiconductor devices therein, be initially intrinsic or doped.
Most importantly, the present invention comprises inverting and non-inverting devices with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems. In use said inverting and non-inverting present invention devices, comprise two oppositely facing electrically interconnected rectifying diodes in intrinsic, or a single doping type semiconductor. A basic feature of present invention devices is that a forward direction of rectification of each of said electrically interconnected oppositely facing rectifying diodes changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor. Said present invention inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprise gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulator, and each has a non-electrically interconnected terminal. In use, different voltages are applied to the non-electrically interconnected terminals of each of the oppositely facing rectifying diodes, and a voltage between said applied different voltages, inclusive, is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored voltage responds as a function of applied gate voltage. Said monitored voltage is essentially electrically isolated from said gate voltage and appears at said electrical interconnection between said two oppositely facing rectifying diodes primarily through the rectifying diode selected from the group consisting of: (both of said two oppositely facing electrically interconnected rectifying diodes), which is caused to be forward biased as a result of semiconductor “doping type” modulation by said applied gate voltage. The basis of operation of said inverting and non-inverting gate voltage channel induced semiconductor devices being that said rectifying junctions are each comprised of material(s) that form a rectifying junction to semiconductor when it is doped either N or P-type by either metalurgical or field induced means.
To aide with understanding of the present invention, an embodiment of an inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complimentary Metal Oxide Semiconductor (CMOS) systems, similar to that disclosed in U.S. Pat. No. 5,663,584 and continuations therefr
Loke Steven
Welch James D.
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