Programmable delay circuit and method with dummy circuit...

Details Programmable delay circuit and method with dummy circuit... Programmable delay circuit and method with dummy circuit...

1999-12-02

2001-06-05

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S270000

Reexamination Certificate

active

06242959

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to programmable delay circuits and operating methods with correction for delay time errors resulting from variations in environmental factors such as temperature and power supply voltage.
2. Description of the Related Art
Programmable delay circuits (PDCs) are commonly employed in applications such as timing interpolators, which require delays that can be adjusted under user control. However, because of signal conditioning required to place the timing reference signal in an appropriate state for the variable delay element, and also to condition the timing reference signal to properly drive outside circuitry, an offset time is introduced into the delay circuit. This offset time varies significantly with changes in environmental factors such as temperature and power supply voltage, and thus adds an error term to the desired delay period. This problem is particularly serious for electronic test equipment, which requires a very low temperature sensitivity.
The general approach to reducing delay offset variations has been to try to design circuit elements with minimum temperature sensitivity. Unfortunately, this can add significantly to both the cost and complexity of the circuit, and does not fully resolve the problem.
SUMMARY OF THE INVENTION
The present invention seeks to provide a PDC which automatically compensates for environmentally induced variations in its delay, in an accurate and effective manner, without adding substantially to the circuit's cost or complexity.
These goals are achieved with a compensated PDC in which a dummy PDC emulates one or more main PDCs in environmental sensitivity. With dynamically changing inputs to the main PDCs but a substantially constant input to the dummy PDC, changes in the dummy PDC's delay are monitored and a correction signal is applied to the dummy PDC to maintain its delay substantially constant. Correction signals which match the dummy circuit's correction signal are also applied to the main PDCs to hold their delays substantially constant in a similar manner.
The dummy circuit compensation is preferably accomplished with a feedback circuit. The feedback circuit could be designed with a wide adjustment range, allowing it to be set to any value within a full period of a reference clock that is substantially less subject to environmentally induced changes than are the main and dummy PDCs. However, a wide feedback range can result in undesirable jitter, limited signal head room and limited refire rates. To avoid these problems, the dummy delay circuit is initially programmed so that its total delay is an integer number of reference clock periods. This allows for a dummy delay path that produces a delayed output coinciding with the rising edge of a clock pulse. Since environmentally induced variations in the offset delay will normally be significantly less than a full clock period, this initial calibration allows the controllable range of the delay path to be made relatively small, thus largely avoiding the adverse effects of a larger controllable range. The calibration can be implemented through programmable digital-to-analog converters which reside in the main and dummy PDCs.
These and other features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.


REFERENCES:
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5124593 (1992-06-01), Michel
patent: 5428309 (1995-06-01), Yamauchi et al.
patent: 5598039 (1997-01-01), Weber
patent: 5719514 (1998-02-01), Sato

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