Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

1998-05-29

2001-01-02

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270

Utility Patent

active

06169692

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory and, more particularly, it relates to a method of erasing a MOS flash memory.
2. The Related Art
FIG. 2
is a cross sectional view of a flash memory cell having a floating gate structure according to the prior art. The flash memory cell comprises a semiconductor substrate
31
, a drain
34
, a source
35
, a control gate
36
and a floating gate
37
. Terminals D, S, G and B are voltage terminals for applying voltage to the drain
34
, the source
35
, the control gate
36
and the semiconductor substrate
31
, respectively.
The flash memory of a channel hot electron type having the structure as shown in
FIG. 2
conducts writing by injecting electrons into the floating gate
37
by utilizing a hot electron phenomenon and conducts erasing by withdrawing electrons in the floating gate
37
.
In the flash memory of the structure shown in
FIG. 2
, a first erasing method comprises generating a tunnel current by setting each of the terminals B and G to the ground potential (hereinafter referred to as GND), and setting the terminal S to a first positive potential (hereinafter referred to as V
PP
) and keeping the terminal D open (open state), thereby emitting electrons from the floating gate
37
to the source
35
. Further, a second erasing method comprises generating a tunnel current by setting the terminal G to a negative potential (hereinafter referred to as V
ER
), the terminal S to a second positive potential (hereinafter referred to as V
CC
), setting the terminal B to GND and keeping the terminal D open, thereby emitting electrons from the floating gate
37
to the source
35
. It is assumed that: GND<V
CC
<V
PP
However, in the first erasing method in
FIG. 2
, since a potential difference is great between the potential for the source
35
(V
PP
) and the potential for the semiconductor substrate
31
(GND), there is a problem that charge is produced by hot electron phenomenon between the source
35
and the semiconductor substrate
31
so that the charge is introduced into an oxide film formed on the semiconductor substrate
31
by inter-band tunneling.
Further, in the second erasing method in
FIG. 2
, while a potential difference between the source
35
and the semiconductor substrate
31
can be decreased, this involves a problem of additionally requiring a circuit for generating a negative voltage V
ER
.
For overcoming the above-described prior art problem, techniques as described in Japanese Patent Laid-Open No. Hei 4-229655 (hereinafter referred to as “Publication 1”) and Japanese Patent Laid-Open No. Hei 5-343700 (hereinafter referred to as “Publication 2”) have been developed.
FIG. 3
is a cross sectional view of a flash memory cell described in Publication 1. A flash memory cell shown in
FIG. 3
comprises a semiconductor substrate
41
, a deep well
42
of a conduction type opposite to that of the semiconductor substrate
41
, a shallow well
43
of a conduction type identical with that of the semiconductor substrate
41
, a drain
44
, a source
45
, a control gate
46
and a floating gate
47
. Further, terminals D, S, G and BB are voltage terminals for applying voltage to the drain
44
, the source
45
, the control gate
46
and the semiconductor substrate
41
respectively. Terminals DW and W are voltage terminals for applying voltage to the deep well
42
and the shallow well
43
respectively, in which the terminal W corresponds to the terminal B in FIG.
2
.
A first erasing method in the flash memory cell of the structure shown in
FIG. 3
comprises withdrawing electrons from the floating gate
47
into the semiconductor substrate
41
while keeping the terminals D and S open, and setting the terminals G and BB to GND and applying V
PP
to the terminals W and DW. This prevents inter-band tunneling between the source
45
and the semiconductor substrate
41
. Further, a second erasing method applies V
ER
to the control gate
46
(terminal G) while setting the potential for the semiconductor substrate
41
(terminal BB) to V
CC
as described in Journal of Solid State Circuits, Vol. 127, No. 11, November 1992: pp 1547-1553.
However, in the first erasing method of Publication 1, in a case of applying V
PP
to the deep well
42
and the shallow well
43
, there is a problem of a withstand voltage between the semiconductor substrate
41
and the wells
42
,
43
. The second erasing method for the second prior art involves a problem of additionally requiring a circuit for generating a negative voltage V
ER
like that the second erasing method in the preceding prior art.
The erasing method of prior art Publication 2 keeps the terminals G, BB to GND by setting the terminals D and DW open, and sets the terminal W to V
CC
, the terminal S to V
PP
and the terminals G and BB to GND of the FIG.
3
. The Publication 2 prior art decreases the potential difference between the source
45
and the semiconductor substrate
41
by setting the terminal W to V
CC
, thereby preventing the inter-band tunneling. The erasing method shown in Publication 2 has a merit, for example, of not requiring a circuit for generating the negative potential V
ER
.
However, the inventor discovered that the erasing method of Publication 2 causes problems to be described below under the following structure.
A MOS transistor formed on a silicon substrate is a 4-terminal device in which a voltage is applied also to a substrate. A contact for applying the voltage to the substrate is formed near the transistor. However, actually, since the memory is disposed while densely arranging memory cells in order to efficiently use a chip, the contact is disposed to the outer circumference of a memory cell array. The situation is identical also in the memory of a triple well structure. Such a structure is shown in FIG.
4
A.
FIGS. 4A and 4B
show a flash memory of a triple well structure in the related art.
FIG. 4A
is a cross sectional view of the flash memory and
FIG. 4B
shows a voltage wave form supplied with each of portions of the flash memory. The flash memory cell of a triple well structure shown in
FIG. 4A
comprises a semiconductor substrate
21
, a deep well
22
of a conduction type opposite to that of the semiconductor substrate
21
, a shallow well
23
of a conduction type identical with that of the semiconductor substrate
21
, drains
241
,
242
, sources
251
,
252
, control gates
261
,
262
and floating gates
271
,
272
. Further, terminals D, S, G and BB are voltage terminals for applying voltage to the drains
241
and
242
, the sources
251
and
252
, the control gates
261
and
262
and the semiconductor substrate
21
, respectively. The terminals DW and W are terminals for applying voltage to the deep well
22
and to the shallow well
23
respectively, the terminal W corresponds to the terminal B in FIG.
2
. Resistor r represents a resistive component of the well
23
and capacitor c represents a parasitic capacitance component between the semiconductor substrate
21
and the well
23
.
Now, a first memory cell comprising the drain
241
, the source
251
, the control gate
261
and the floating gate
271
is formed at the end of a well (memory cell array). A second memory cell comprising the drain
242
, the source
252
, the control gate
262
and the floating gate
272
is formed at a central portion of the well (memory cell array).
A structure comprising the semiconductor substrate
21
, the deep well
22
and the shallow well
23
shown in the related art has a high resistance since the doping amount of impurities is small. Accordingly, as shown in
FIG. 4A
, a delay for the change of the potential is caused in a portion Y of the semiconductor substrate of the second memory cell at the central portion of the memory cell array due to the resistor r and the parasitic capacitance c, compared with that in a portion X of with the semiconductor substrate of the first memory cell at the end of the memory cell array when the voltage is applied to the

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