Package structure for semiconductor chip

Details Package structure for semiconductor chip Package structure for semiconductor chip

1999-03-04

2001-08-28

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With heat sink embedded in encapsulant

C257S778000, C257S780000, C257S691000, C257S717000, C257S720000, C257S795000

Reexamination Certificate

active

06281592

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package structure for a semiconductor chip, including a substrate on which a semiconductor chip is mounted via an underfiller filling between the substrate and the chip.
2. Description of the Related Art
FIGS. 11 and 12
show a known package structure of a semiconductor chip.
A substrate
10
has pads
12
formed thereon and a semiconductor chip
20
has electrodes connected by soldering etc. to the pads
12
through bumps
30
of solder or the like. An underfiller
40
of a cured resin fills a space between the semiconductor chip
20
and the underlying substrate
10
and also bonds the semiconductor chip
20
and the substrate
10
. The substrate
10
is formed of epoxy or an other resin having a low permittivity and has circuit wiring (not shown) formed thereon and designed for transmitting high frequency signals without significant loss.
When a thermal stress is generated by a difference between thermal expansion coefficients of the semiconductor chip
20
, typically of silicon, and the substrate
10
, of resin, and acts between the chip
20
and the substrate
10
, the underfiller
40
bonding the chip
20
and the substrate
10
prevents separation between the pads
12
of the substrate
10
and the electrodes of the chip
20
, in which the electrodes are connected to the pads
12
through the bumps
30
, to ensure good electrical connection between the semiconductor chip
20
and the pads
12
.
The underfiller
40
consists of a resin containing a small amount of filler agents such as silicone and having good fluidity, because a space between the semiconductor chip
20
and the substrate can be as small as 80 to 100 &mgr;m and a resin to be filled in the space must have a low viscosity, i.e., a high fluidity.
However, an underfiller
40
formed by curing a resin containing a small amount of filler agents and having a high fluidity has a thermal expansion coefficient greater than that of the semiconductor chip
20
or the resin substrate
10
.
For example, a semiconductor chip
20
of silicon has a thermal expansion coefficient of 3.4 ppm/° C. and a substrate
10
of an FR-4 resin has a thermal expansion coefficient of 15 ppm/° C., whereas the above-mentioned underfiller
40
has a thermal expansion coefficient of 23 ppm/° C.
When the semiconductor chip
20
, the underfiller
40
and the substrate
10
are subject to heat generated by the semiconductor chip
20
etc., the differencs between thermal expansion coefficients of these three members generates thermal stress between these three members to cause distortion of the substrate
10
such that upward depression in the form of an arc etc. occurs in the lower surface of the substrate
10
in a portion underneath the semiconductor chip
20
, so that electrical connection cannot properly achieved between pads on the depressed lower surface of the semiconductor chip
20
and pads on a separate mother board. The thermal stress acting between the substrate
10
and the underfiller
40
can also cause fracture of the fragile semiconductor chip
20
.
In the conventional package structure shown in
FIGS. 11 and 12
, a rectangular frame
50
of copper or other stiff metal is secured on the substrate
10
to surround the portion of the substrate
10
in which the semiconductor chip
20
is mounted, thereby mitigating thermal stress exerted on the substrate
10
.
However, this cannot provide a satisfactory solution to the problems that depression occurs in the lower surface of the substrate
10
in a portion underneath the semiconductor chip
20
or that large stress is exerted on the semiconductor chip
20
. This is particularly significant for the case in which a large size semiconductor chip
20
having sides of 10 mm or more is mounted on a thin substrate
10
.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an improved package structure of a semiconductor chip, including a resin substrate having pads formed thereon, a semiconductor chip having electrodes connected to the pads through bumps, and an underfiller filling a space between the semiconductor chip and the resin substrate and bonding the semiconductor chip to the resin substrate, in which thermal stress acting between the semiconductor chip, the underfiller and the substrate is either mitigated or absorbed so as to solve the conventional problems that upward depression occurs in the lower surface of the substrate in a portion underneath the semiconductor chip or that the semiconductor chip fractures.
To achieve the object according to the first aspect of the present invention, there is provided a package structure of a semiconductor chip, comprising:
a resin substrate having pads formed thereon,
a semiconductor chip having electrodes connected to the pads through bumps,
an underfiller filling a space between the semiconductor chip and the resin substrate and bonding the semiconductor chip to the resin substrate, and
a stiffener buried in the resin substrate in a portion underneath the semiconductor chip to mitigate a thermal stress acting between the semiconductor chip, the underfiller and the resin substrate.
In the package structure of the first aspect, when heat generated by the semiconductor chip etc. generates thermal stress between the semiconductor chip, the underfiller and the substrate having different thermal expansion coefficients, the stiffener made of a stiff material and buried in the substrate in a portion underneath the semiconductor chip mitigates the thermal stress acting between the semiconductor chip and the underfiller and prevents upward depression of the lower surface of the substrate in a portion underneath the semiconductor chip or prevents fracture of the semiconductor chip.
In a preferred embodiment, the stiffener has a thermal expansion coefficient smaller than that of the substrate so that the substrate in the portion underneath the semiconductor chip apparently has a reduced thermal expansion coefficient, or a thermal expansion coefficient close to that of the semiconductor chip, to reduce the thermal stress acting between the substrate, the underfiller and the semiconductor chip.
In a preferred embodiment, the stiffener is composed of separate segments buried in the substrate in portions underneath corners of the semiconductor chip so that thermal stress concentrated at the chip corners can be efficiently mitigated by the stiffener buried in the substrate in portions underneath the chip corners. It is also advantageous that a circuit wiring can be formed in the substrate in portions other than the substrate portions underneath the chip corners without intersection with the stiffener to avoid electrical short circuit between the circuit wiring and the stiffener.
In a preferred embodiment, the stiffener forms a single frame buried in the substrate in a portion underneath a periphery of the semiconductor chip so that thermal stress concentrated at the chip corners can be efficiently mitigated by the stiffener portions located underneath the chip corners, and at the same time, mitigation of the thermal stress at the chip corners can be substantially effected by dispersion of thermal stress over the adjoining stiffener portions other than the stiffener portions located underneath the chip corners, to further promote mitigation of thermal stress concentrated at the chip corners by dispersing the thermal stress entirely over the stiffener.
In a preferred embodiment, the stiffener forms a broad plate buried in the substrate in a portion underneath the whole of the semiconductor chip so that thermal stress concentrated at corners of the semiconductor chip can be efficiently mitigated by the stiffener portions underneath the chip corners, and at the same time, mitigation of the thermal stress at the chip corners can be substantially effected by dispersion of thermal stress broadly over the stiffener portions other than the stiffener portions underneath the chip corners, to still further promote mitigation of thermal stress concentrat

Affiliated with

Also associated with

Rating

Package structure for semiconductor chip does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Package structure for semiconductor chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Package structure for semiconductor chip will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2481000