Process for forming an edge structure to seal integrated...

Details Process for forming an edge structure to seal integrated... Process for forming an edge structure to seal integrated...

2000-03-24

2001-04-03

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C438S763000, C438S958000

Reexamination Certificate

active

06210994

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit manufacturing, and, more particularly, to a process for the formation of a peripheral morphological structure designed to seal integrated electronic devices and the associated devices.
Specifically reference is made to a process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material of the type calling for formation over the major surface of at least one dielectric multilayer. The dielectric multilayer comprises a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a first area more internal and a second area more external in the morphological structure.
BACKGROUND OF THE INVENTION
As is well known, electronic devices, in particular those integrated monolithically, if not carefully protected and sealed can be affected critically by the environmental conditions in which they are placed during assembly and/or during their lifetimes. In particular, the presence of humidity and other contaminating agents can result in the entry of undesired materials into the electrically active part of the device. This generally reduces the reliability of the device and can even irreversibly compromise its operation.
It is therefore crucial, especially for certain applications, to make the best possible provision for protection and sealing of the electrical circuit which is part of the device. For this purpose it is necessary to ensure perfect sealing also at the edge of the device.
For the meaning of edge of a device it should be remembered that a plurality of identical monolithically integrated circuits are formed simultaneously on a single wafer of semiconductor material, commonly monocrystalline silicon, in adjacent prepared areas. The individual devices are spaced and separated by unoccupied cross strips in which the surface of the silicon is left exposed. These strips are typically mutually orthogonal and are known as “scribe lines” and the wafer will be cut through them mechanically to separate the individual devices (the so-called “dicing” process). The edge of a device is thus the peripheral region thereof bordering on the associated scribe line.
After formation of the circuit electrical structures, i.e., of the electrical components, such as, for example, transistors or memory cells and their interconnections, the device is insulated and sealed. Layers of dielectric materials act as electrical and thermal insulators of the conducting interconnection layers and protect the underlying structures of the integrated circuit from mechanical stress, such as impacts or from contaminants (impurities, moisture), thereby creating a barrier against those harmful substances coming from the external environment.
The so-called final passivation typically includes a relatively thick layer completely covering the device to protect it. However, at the edge of the device the presence of the final passivation alone is not sufficient to ensure its sealing. Other measures are necessary. Primarily for this purpose, the most peripheral structures of the device are typically left inactive, i.e. disconnected electrically from the device terminals.
More specifically, for protection of the device at the edges there is formed a structure arranged peripherally which also permits sealing of the device. This is a device edge morphological structure and reference will be made thereto in the following description. It includes a closed ring completely surrounding the device along its entire periphery. This structure is known to those skilled in the art as Chip Outline Band (COB), i.e., a band surrounding the device.
The device edge morphological structure is formed simultaneously with the electrical structures of the integrated circuit. The more internal part of the COB, i.e. the part nearest the device, does indeed normally include structures which appear morphologically identical to the electrically active ones of the device. Moreover they do not have any electrical function since they are electrically insulated, but only act as termination for the device. The COB structure is consequently different in different devices depending on the process used and the device design.
In any case the most external part of the COB, which terminates in the scribe line adjacent to and is contiguous with the preceding part, is designed so as to completely seal the device from the external environment. For this purpose there is applied the simple principle in accordance with which to permit better sealing each overlying layer must be terminated further externally than the one immediately below. The layers are disposed to virtually cover back each other. This way the edge descends gradually downward while going near the associated scribe line, such as to enclose the integrated circuit several times in subsequent shells.
An example of a device edge structure of the known type is shown in FIG.
1
. Specifically, there is represented in cross-section, not to scale, a peripheral portion of a single device. By way of example the device is of the type formed by a CMOS process with two polysilicon levels. In particular, reference is made by way of example to a device, such as a non-volatile memory typically of the EEPROM or FLASH type.
In addition, the device comprises specifically two interconnection levels. Indeed it should be remembered that two or more interconnection levels are typically provided in the more complex integrated circuits to limit the area occupied by reducing the size of the components, and, thus, of the device to thereby increase the total number of devices which can be integrated on a single wafer.
The device has been sectioned from the interior to the exterior along a line parallel to an edge. In particular, the section line passes along a source-drain line of memory cells. In
FIG. 1
the visible portion of the device edge morphological structure is indicated as a whole by reference number
1
. Further to the right of the figure is seen a scribe line of which the visible part is indicated by reference number
2
. On the left the device edge morphological structure joins the active part of the device i.e. the actual electronic circuit (not shown in
FIG. 1
) of which it defines an extension with continuity. It should be remembered that the device edge morphological structure is shown in its most peripheral region, while in some cases another portion thereof comprising other electrically inactive structures could be present at the device periphery.
In
FIG. 1
for greater clarity the COB is divided approximately and ideally into two regions as set forth above. A region indicated by reference number
3
is placed more internally with respect to the circuit and comprises structures morphologically identical to those of the circuit, but not electrically active and providing a sort of extension with continuity of the device circuit structures, and a region
4
which is more external or peripheral having a structure which more correctly has a device sealing function.
The device is formed in a major surface
5
of a substrate
6
of monocrystalline silicon. The process calls for simultaneous formation of the actual circuit and its edge morphological structure. Primarily on the major surface
5
are formed so-called field oxide insulation regions which are indicated by reference number
7
and define active area regions
8
.
Internally to the active area are then formed the circuit structures, such as transistors and memory cells, i.e., floating gate transistors. In region
3
and in particular at the left termination of
FIG. 1
is visible a structure similar to that of a memory cell along the source-drain direction and indicated as a whole by reference number
9
.
The process for forming the circuit components comprises schematically the following steps:
growing in the active area regions a thin tunnel oxide, indicated by reference number
10
, for the memory

Affiliated with

Also associated with

Rating

Process for forming an edge structure to seal integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming an edge structure to seal integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming an edge structure to seal integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2480877