Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1997-12-31
2001-01-16
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C365S226000
Reexamination Certificate
active
06175262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a booster circuit especially meant for generating a voltage of control of the word lines of a dynamic memory.
2. Discussion of the Related Art
FIG. 1
shows two cells of a dynamic memory associated with a conventional booster circuit. Each cell includes a capacitor
10
connected between a fixed potential, such as a low supply potential GND, and the source of a MOS-type N-channel access transistor
12
. The drains of the transistors
12
are connected to respective bit lines BL. The gates of the access transistor
12
associated with the cells forming a word are connected to a common word line WL. A word line WL is generally selected via a P-channel MOS transistor
14
, the gate of which is controlled by a word selection signal WS. The drain of transistor
14
is connected to word line WL and the source of this transistor receives a selection voltage Vpp.
When a
1
is written into a cell, supply voltage Vdd of the memory is presented on the corresponding bit line BL and transistor
14
is turned on. Voltage Vpp is thus presented, without any drop, on word line WL, whereby the access transistors
12
are turned on.
For a memory cell to be able to keep a value
1
as long as possible, capacitors
10
should be changed to the highest possible value, that is, to value Vdd of the supply voltage. Thus, voltage Vpp applied on the gates of transistors
12
must be higher than or equal to Vdd+Vt, where Vt is the gate-source threshold voltage of transistors
12
. This is what the booster circuit enables to obtain.
The booster circuit of
FIG. 1
includes a capacitor
16
, a terminal of which is connected to ground GND and the other terminal of which, providing voltage Vpp, is connected to the cathodes of two diodes
18
and
19
. The anodes of diodes
18
and
19
are connected to potential Vdd by two respective N-channel MOS transistors
21
and
22
. The gate of transistor
22
is connected to the anode of diode
18
, while the gate of transistor
21
is connected to the anode of diode
19
. A capacitor
24
is connected between the anode of diode
18
and a terminal receiving a clock signal CK. A capacitor
25
is connected between the anode of diode
19
and a terminal receiving a clock signal CK*, complementary to signal CK.
Such a booster circuit supplies a voltage Vpp equal to 2Vdd−Vt in the steady state, value Vt being the threshold of diodes
18
and
19
which are generally formed of diode-connected MOS transistors.
During a first half clock period, signal CK is on zero and signal CK* is on
1
(at potential Vdd). The anode of diode
19
, as indicated, is at a potential 2Vdd since capacitor
25
has been charged to Vdd during the preceding half-period. If the voltage of capacitor
16
is lower than 2Vdd−Vt, loads are transferred from capacitor
25
to capacitor
16
via diode
19
, which tend to restore the voltage of capacitor
16
to 2Vdd−Vt.
Transistor
21
is on and is likely to provide, on its source, and thus on the anode of diode
18
, a potential 2Vdd−Vt. The drain of transistor
21
being connected to potential Vdd, transistor
21
only provides, as indicated, potential Vdd to the anode of diode
18
and charges capacitor
24
to Vdd. The gate-source voltage of transistor
22
being negative, transistor
22
is nonconductive.
During the second half clock period, the states of the nodes are symmetrical, that is, signals CK and CK* and the anodes of transistors
18
and
19
are respectively on Vdd, 0, 2Vdd, and Vdd. Transistor
21
is then nonconductive and transistor
22
is on.
It appears that, in this booster circuit, as in other conventional booster circuits, such as that described in U.S. Pat. No. 5,406,523, the gates of N-channel MOS transistors receive a voltage which is substantially twice as high as the supply voltage of the circuit. This is unacceptable if it is desired to implement a dynamic memory in recent CMOS technologies, since the gate oxides are particularly thin and are likely to breakdown if the gate voltage exceeds the supply voltage of the circuit by a large amount. The breakdown risk essentially concerns N-channel MOS transistors since their substrate is connected to ground GND and the breakdown depends on the gate-substrate voltage. The problem is less critical for P-channel MOS transistors, the well of which can be freely connected to any potential.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a booster circuit in which the gate voltages of the MOS transistors can be limited to values acceptable in recent CMOS technologies.
To achieve this and other objects, the present invention provides a booster circuit including a first MOS transistor of a first conductivity type, the source of which is connected to a high voltage line; a second MOS transistor of a second conductivity type, the drain of which is connected to a first supply potential and the source of which is connected to the drain of the first transistor; a first capacitor connected between the gate of the first transistor and a reception terminal for a first clock signal; a second capacitor connected between the gate of the second transistor and the reception terminal for the first clock signal; a third capacitor connected between the drain of the first transistor and a reception terminal for a second clock signal, complementary to the first clock signal; a first one-way precharge means for the first capacitor from the high voltage line, ensuring, during a precharge, that a voltage sufficient to turn on the first transistor is established; and a second one-way precharge means for the second capacitor.
According to an embodiment of the present invention, the first precharge means includes two diodes connected in series between the source and the gate of the first transistor and the second precharge means includes a diode connected between the drain and the gate of the second transistor.
According to an embodiment of the present invention, the circuit includes means for limiting the gate voltage of the second transistor.
According to an embodiment of the present invention, the limiting means is a diode connected in antiparallel to the second precharge means.
According to an embodiment of the present invention, the circuit includes a diode, connected in antiparallel to the first precharge means for limiting the gate voltage of the first transistor.
According to an embodiment of the present invention, the high voltage line exhibits a high capacitance with respect to that of the third transistor.
According to an embodiment of the present invention, the second clock signal exhibits at least one delayed edge with respect to a corresponding edge of the first clock signal.
According to an embodiment of the present invention, the circuit includes a comparator connected to stop an oscillator providing the first and second clock signals when the high voltage reaches a predetermined threshold.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 5270588 (1993-12-01), Choi
patent: 5546296 (1996-08-01), Savignae et al.
patent: 5757228 (1998-05-01), Furutani et al.
patent: 5796293 (1998-08-01), Yoon et al.
patent: 5812017 (1998-09-01), Golla et al.
patent: 5831470 (1998-11-01), Park et al.
patent: 0 727 869 (1996-08-01), None
“Charge Pump Circuit”, IBM Technical Disclosure Bulletin, vol. 33, No. 4, Sep. 1990, pp. 147-148.
Novosel David
Savelli Laurent
Galanthay Theodore E.
Kim Jung Ho
Morris James H.
SGS-Thomson Microelectronics S.A.
Wolf Greenfield & Sacks P.C.
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